Texas Instruments TSB12LV26 manual ±6. PCI Interface Control Terminals, Pcic BE0, Irdy, Pcitrdy

Page 18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2±6. PCI Interface Control Terminals

 

TERMINAL

 

I/O

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NAME

 

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI_C/

 

 

 

 

 

 

 

 

 

 

 

65

 

 

 

 

 

 

 

 

 

 

 

 

 

BE0

 

 

 

 

 

 

PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI

 

PCI_C/BE1

 

53

 

 

 

I/O

terminals. During the address phase of a bus cycle PCI_C/BE3±PCI_C/BE0 defines the bus command. During

 

PCI_C/BE2

 

41

 

 

 

the data phase, this 4-bit bus is used as byte enables.

 

PCI_C/BE3

 

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock run. This terminal provides clock control through the

 

 

protocol. An internal pulldown

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI_CLKRUN

 

PCI_CLKRUN

 

 

7

I/O

resistor is implemented on this terminal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This terminal is implemented as open-drain.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI device select. The TSB12LV26 asserts this signal to claim a PCI cycle as the target device. As a PCI

 

PCI_DEVSEL

 

 

47

I/O

initiator, the TSB12LV26 monitors this signal until a target responds. If no target responds before time-out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

occurs, then the TSB12LV26 terminates the cycle with an initiator abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle.

 

 

is asserted to indicate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI_FRAME

 

PCI_FRAME

 

 

43

I/O

that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is deasserted, the PCI bus transaction is in the final data phase.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV26 access to the PCI bus after

 

PCI_GNT

 

 

 

 

 

 

14

I

the current data transaction has completed. This signal may or may not follow a PCI bus request, depending

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

upon the PCI bus parking algorithm.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI_IDSEL

 

29

I

Initialization device select. IDSEL selects the TSB12LV26 during configuration space accesses. IDSEL can be

 

 

connected to one of the upper 24 PCI address lines on the PCI bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI initiator ready.

 

indicates the ability of the PCI bus initiator to complete the current data phase of the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRDY

 

PCI_IRDY

 

 

 

 

44

I/O

transaction. A data phase is completed upon a rising edge of PCLK where both PCI_IRDY and PCI_TRDY are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

asserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI parity. In all PCI bus read and write cycles, the TSB12LV26 calculates even parity across the AD and C/BE

 

 

PCI_PAR

 

52

I/O

buses. As an initiator during PCI cycles, the TSB12LV26 outputs this parity indicator with a one PCI_CLK delay.

 

 

As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

can result in a parity error assertion (PCI_PERR).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match

 

PCI_PERR

 

49

I/O

 

 

PCI_PAR when PERR_ENB (bit 6) is set in the PCI command register (offset 04h, see Section 3.4).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

O

Power management event. This terminal indicates wake events to the host.

 

PCI_PME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus request. Asserted by the TSB12LV26 to request access to the bus as an initiator. The host arbiter

 

PCI_REQ

 

15

O

 

 

asserts the PCI_GNT signal when the TSB12LV26 has been granted access to the bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI system error. When SERR_ENB (bit 8) in the PCI command register (offset 04h, see Section 3.4) is set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the output is pulsed, indicating an address parity error has occurred. The TSB12LV26 needs not be the target

 

PCI_SERR

 

51

O

 

 

of the PCI cycle to assert this signal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This terminal is implemented as open-drain.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus

 

PCI_STOP

 

 

 

48

I/O

transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

not support burst data transfers.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI target ready.

 

 

 

indicates the ability of the PCI bus targer to complete the current data phase of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI_TRDY

 

PCI_TRDY

 

 

45

I/O

the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI_TRDY are asserted.

2±6

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables ViiViii Features DescriptionOrdering Number Name Voltage Package Related DocumentsOrdering Information OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC CCP±1. Signals Sorted by Terminal Number Terminal Name±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name Pciclk ±4. PCI System TerminalsPCIRST, terminal As open-drainDuring the data phase, AD31±AD0 contain data ±5. PCI Address and Data TerminalsIrdy ±6. PCI Interface Control TerminalsPcic BE0 Pcitrdy±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning±1. TSB12LV26 Block Diagram Vendor ID Register PCI Configuration Registers±2. PCI Configuration Register Map Register Name Offset±3. Command Register Description Command RegisterCommand Device ID RegisterStatus Register Status±4. Status Register Description Class Code and Revision ID Register Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class code and revision IDHeader Type and Bist Register Ohci Base Address RegisterTI extension base address TI Extension Base Address RegisterSubsystem Identification Register Subsystem identificationInterrupt Line and Pin Register Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Register Interrupt line and pinMingnt and Maxlat Register Ohci Control RegisterNextitem Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer CapabilityidPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power management control and status Power Management Control and Status RegisterPower Management Extension Register Power management extensionMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description ±19. Subsystem Access Register Description Subsystem Access RegisterSubsystem access SubdevidGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom PhysicalRequestFilterHiClear IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet Physical request filter low PhysicalRequestFilterLoSetCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Isochronous transmit context commandIsochronous receive context command Asynchronous context control ContextControlSetOhci Version Register Ohci version±2. Ohci Version Register Description Guid ROM Guid ROM Register±3. Guid ROM Register Description RSUAsynchronous transmit retries Asynchronous Transmit Retries RegisterCSR Data Register ±4. Asynchronous Transmit Retries Register DescriptionCSR compare CSR Compare RegisterCSR Control Register CSR control±6. Configuration ROM Header Register Description Configuration ROM Header RegisterConfiguration ROM header Bus Identification RegisterBus Options Register Bus options±7. Bus Options Register Description Guid high Guid High RegisterGuid Low Register Guid low±8. Configuration ROM Mapping Register Description Configuration ROM Mapping RegisterConfiguration ROM mapping Posted Write Address Low Register±9. Posted Write Address High Register Description Posted Write Address High RegisterPosted write address high Vendor IDHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self ID-buffer pointer Self-ID Buffer Pointer RegisterSelf-ID Count Register Self-ID countIsochronous Receive Channel Mask High Register Isochronous receive channel mask highIsochronous Receive Channel Mask Low Register Isochronous receive channel mask lowInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrs Rscu Arrq Rscu±15. Interrupt Mask Register Description Interrupt Mask RegisterInterrupt mask Rscu RSCIsochronous Transmit Interrupt Event Register Isochronous transmit interrupt event±21 Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask Isochronous transmit interrupt maskIsochronous receive interrupt event Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt mask±18. Fairness Control Register Description Fairness Control RegisterFairness control Fairness controlLink Control Register Link control±19. Link Control Register Description ±20. Node Identification Register Description Node Identification RegisterNode identification CPSPHY Layer Control Register PHY layer control±21. PHY Control Register Description ±22. Isochronous Cycle Timer Register Description Isochronous Cycle Timer RegisterIsochronous cycle timer 24±12Asynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 ±24. Asynchronous Request Filter Low Register Description Asynchronous Request Filter Low RegisterAsynchronous request filter low ±30±25. Physical Request Filter High Register Description Physical Request Filter High RegisterPhysical request filter high Are accepted±32 ±26. Physical Request Filter Low Register Description Physical Request Filter Low RegisterPhysical request filter low Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34±27. Asynchronous Context Control Register Description Asynchronous Context Control RegisterAsynchronous context control Rscu RSUAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous Receive Context Control Register Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous receive context controlMultiChanMode CycleMatchEnableReserved. Bits 27±16 return 0s when read Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous receive context match When the command descriptor w field is set to 11bIsochronous Receive Context Match Register ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges²Recommended Operating Conditions Operation MIN NOMUnit Operation Test MIN MAX Unit Conditions Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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