Texas Instruments TSB12LV26 manual Host Controller Control Register, Host controller control

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4.16 Host Controller Control Register

The host controller control set/clear register pair provides flags for controlling the TSB12LV26. See Table 4±10 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

 

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Host controller control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

RSC

R

R

R

R

R

 

R

RC

RSC

R

R

RSC

RSC

RSC

RSCU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

X

0

0

0

0

0

0

0

0

0

0

0

X

0

0

Bit

15

 

14

13

12

11

 

10

9

8

7

 

6

5

4

 

3

2

1

0

Name

 

 

 

 

 

 

 

 

 

Host controller control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

R

 

R

R

 

R

R

 

R

R

R

 

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

0

 

0

0

 

0

0

 

0

0

0

 

0

0

0

0

 

Register:

Host controller control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only

 

 

 

 

 

Offset:

 

50h

set register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

54h

clear register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

X00X 0000h

 

 

 

Table 4±10. Host Controller Control Register Description

 

 

 

 

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

 

31

RSVD

 

R

Reserved. Bit 31 returns 0 when read.

 

 

 

 

 

30

noByteSwapData

RSC

This bit is used to control whether physical accesses to locations outside the TSB12LV26 itself as

well as any other DMA data accesses should be swapped.

 

 

 

 

 

 

 

 

 

29±24

RSVD

 

R

Reserved. Bits 29±24 return 0s when read.

 

 

 

 

 

 

 

 

 

This bit informs upper level software that lower level software has consistently configured the

 

 

 

 

P1394a enhancements in the Link and PHY. When this bit is 1, generic software such as the OHCI

23

programPhyEnable

RC

driver is responsible for configuring P1394a enhancements in the PHY and bit 22

(aPhyEnhanceEnable) in the TSB12LV26. When this bit is 0, the generic software may not modify

 

 

 

 

 

 

 

 

the P1394a enhancements in the TSB12LV26 or PHY and cannot interpret the setting of bit 22

 

 

 

 

(aPhyEnhanceEnable). This bit is initialized from serial EEPROM.

 

 

 

 

 

 

 

 

 

When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set this bit to

22

aPhyEnhanceEnable

RSC

use all P1394a enhancements. When bit 23 (programPhyEnable) is set to 0, the software does

 

 

 

 

not change PHY enhancements or this bit.

 

 

 

 

 

21±20

RSVD

 

R

Reserved. Bits 21±20 return 0s when read.

 

 

 

 

 

19

LPS

 

RSC

This bit is used to control the link power status. Software must set this bit to 1 to permit link-PHY

 

communication. A 0 prevents link-PHY communication.

 

 

 

 

 

 

 

 

 

18

postedWriteEnable

RSC

This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only

when bit 17 (linkEnable) is 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is cleared to 0 by either a hardware or software reset. Software must set this bit to 1 when

 

 

 

 

the system is ready to begin operation and then force a bus reset. This bit is necessary to keep

17

linkEnable

 

RSC

other nodes from sending transactions before the local system is ready. When this bit is cleared,

 

 

 

 

the TSB12LV26 is logically and immediately disconnected from the 1394 bus, no packets are

 

 

 

 

received or processed nor are packets transmitted.

 

 

 

 

 

 

 

 

 

When this bit is set, all TSB12LV26 states are reset, all FIFOs are flushed, and all OHCI registers

16

SoftReset

 

RSCU

are set to their hardware reset values unless otherwise specified. PCI registers are not affected by

 

this bit. This bit remains set while the soft reset is in progress and reverts back to 0 when the reset

 

 

 

 

 

 

 

 

has completed.

 

 

 

 

 

15±0

RSVD

 

R

Reserved. Bits 15±0 return 0s when read.

 

 

 

 

 

4±13

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage PackageCCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC VccpTerminal Name ±1. Signals Sorted by Terminal Number±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers±2. PCI Configuration Register Map Vendor ID RegisterDevice ID Register Command RegisterCommand ±3. Command Register DescriptionStatus Register Status±4. Status Register Description Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID RegisterOhci Base Address Register Header Type and Bist RegisterSubsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base addressRegister Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin RegisterOhci Control Register Mingnt and Maxlat RegisterCapabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer NextitemPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and statusMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register DescriptionGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClearAsynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatchOhci Version Register Ohci version±2. Ohci Version Register Description RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retriesCSR control CSR Compare RegisterCSR Control Register CSR compareBus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register DescriptionBus Options Register Bus options±7. Bus Options Register Description Guid low Guid High RegisterGuid Low Register Guid highPosted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register DescriptionVendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register DescriptionHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointerIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrq Rscu Arrs RscuRscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register DescriptionIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt eventFairness control Fairness Control RegisterFairness control ±18. Fairness Control Register DescriptionLink Control Register Link control±19. Link Control Register Description CPS Node Identification RegisterNode identification ±20. Node Identification Register DescriptionPHY Layer Control Register PHY layer control±21. PHY Control Register Description 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register DescriptionAsynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register DescriptionAre accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description±32 Physical request filter low Physical Request Filter Low RegisterPhysical request filter low ±26. Physical Request Filter Low Register Description±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper boundRscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register DescriptionAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control RegisterMatch register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsRecommended Operating Conditions Operation MIN NOMUnit Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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