Texas Instruments TSB12LV26 manual Mingnt and Maxlat Register, Ohci Control Register

Page 30

3.14 MIN_GNT and MAX_LAT Register

The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of bits 15±8 of the latency timer and class cache line size register (offset 0Ch, see Section 3.7). If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. See Table 3±11 for a complete description of the register contents.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

MIN_GNT and MAX_LAT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

Register: MIN_GNT and MAX_LAT

Type: Read/Update

Offset: 3Eh

Default: 0402h

Table 3±11. MIN_GNT and MAX_LAT Register Description

BIT

FIELD NAME

TYPE

 

DESCRIPTION

 

 

 

 

 

 

 

Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration

15±8

MAX_LAT

RU

priority-level to the TSB12LV26. The default for this register indicates that the TSB12LV26 may need to

access the PCI bus as often as every 0.25

∝s; thus, an extremely high priority level is requested. The

 

 

 

 

 

 

contents of this field may also be loaded through the serial ROM.

 

 

 

 

 

 

 

Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer and class

7±0

MIN_GNT

RU

cache line size register (offset 0Ch, see Section 3.7) value to the TSB12LV26. The default for this register

indicates that the TSB12LV26 may need to sustain burst transfers for nearly 64 ∝s; thus, requesting a large

 

 

 

 

 

 

value be programmed in bits 15±8 of the TSB12LV26 latency timer and class cache line size register.

3.15 OHCI Control Register

The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 3±12 for a complete description of the register contents.

Bit

31

 

30

 

29

 

28

 

27

26

25

24

23

 

22

21

 

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

OHCI control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R

 

R

 

R

R

R

R

R

 

R

R

 

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

0

 

0

0

0

0

0

 

0

0

 

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

15

 

14

 

13

 

12

 

11

10

9

8

7

 

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

OHCI control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R

 

R

 

R

R

R

R

R

 

R

R

 

R

R

R

R

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

0

 

0

0

0

0

0

 

0

0

 

0

0

0

0

0

 

 

Register:

OHCI control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

 

40h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3±12. OHCI Control Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

 

TYPE

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31±1

 

RSVD

 

 

R

Reserved. Bits 31±1 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

GLOBAL_SWAP

 

 

R/W

When this bit is set, all quadlets read from and written to the PCI interface are byte swapped (big

 

 

 

endian). This bit is loaded from ROM and should be programmed to 0 for normal operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±10

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables ViiViii Features DescriptionOrdering Number Name Voltage Package Related DocumentsOrdering Information OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC CCP±1. Signals Sorted by Terminal Number Terminal Name±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name Pciclk ±4. PCI System TerminalsPCIRST, terminal As open-drainDuring the data phase, AD31±AD0 contain data ±5. PCI Address and Data TerminalsIrdy ±6. PCI Interface Control TerminalsPcic BE0 Pcitrdy±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning±1. TSB12LV26 Block Diagram Vendor ID Register PCI Configuration Registers±2. PCI Configuration Register Map Register Name Offset±3. Command Register Description Command RegisterCommand Device ID RegisterStatus Register Status±4. Status Register Description Class Code and Revision ID Register Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class code and revision IDHeader Type and Bist Register Ohci Base Address RegisterTI extension base address TI Extension Base Address RegisterSubsystem Identification Register Subsystem identificationInterrupt Line and Pin Register Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Register Interrupt line and pinMingnt and Maxlat Register Ohci Control RegisterNextitem Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer CapabilityidPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power management control and status Power Management Control and Status RegisterPower Management Extension Register Power management extensionMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description ±19. Subsystem Access Register Description Subsystem Access RegisterSubsystem access SubdevidGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom PhysicalRequestFilterHiClear IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet Physical request filter low PhysicalRequestFilterLoSetCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Isochronous transmit context commandIsochronous receive context command Asynchronous context control ContextControlSetOhci Version Register Ohci version±2. Ohci Version Register Description Guid ROM Guid ROM Register±3. Guid ROM Register Description RSUAsynchronous transmit retries Asynchronous Transmit Retries RegisterCSR Data Register ±4. Asynchronous Transmit Retries Register DescriptionCSR compare CSR Compare RegisterCSR Control Register CSR control±6. Configuration ROM Header Register Description Configuration ROM Header RegisterConfiguration ROM header Bus Identification RegisterBus Options Register Bus options±7. Bus Options Register Description Guid high Guid High RegisterGuid Low Register Guid low±8. Configuration ROM Mapping Register Description Configuration ROM Mapping RegisterConfiguration ROM mapping Posted Write Address Low Register±9. Posted Write Address High Register Description Posted Write Address High RegisterPosted write address high Vendor IDHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self ID-buffer pointer Self-ID Buffer Pointer RegisterSelf-ID Count Register Self-ID countIsochronous Receive Channel Mask High Register Isochronous receive channel mask highIsochronous Receive Channel Mask Low Register Isochronous receive channel mask lowInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrs Rscu Arrq Rscu±15. Interrupt Mask Register Description Interrupt Mask RegisterInterrupt mask Rscu RSCIsochronous Transmit Interrupt Event Register Isochronous transmit interrupt event±21 Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask Isochronous transmit interrupt maskIsochronous receive interrupt event Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt mask±18. Fairness Control Register Description Fairness Control RegisterFairness control Fairness controlLink Control Register Link control±19. Link Control Register Description ±20. Node Identification Register Description Node Identification RegisterNode identification CPSPHY Layer Control Register PHY layer control±21. PHY Control Register Description ±22. Isochronous Cycle Timer Register Description Isochronous Cycle Timer RegisterIsochronous cycle timer 24±12Asynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 ±24. Asynchronous Request Filter Low Register Description Asynchronous Request Filter Low RegisterAsynchronous request filter low ±30±25. Physical Request Filter High Register Description Physical Request Filter High RegisterPhysical request filter high Are accepted±32 ±26. Physical Request Filter Low Register Description Physical Request Filter Low RegisterPhysical request filter low Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34±27. Asynchronous Context Control Register Description Asynchronous Context Control RegisterAsynchronous context control Rscu RSUAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous Receive Context Control Register Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous receive context controlMultiChanMode CycleMatchEnableReserved. Bits 27±16 return 0s when read Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous receive context match When the command descriptor w field is set to 11bIsochronous Receive Context Match Register ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges²Recommended Operating Conditions Operation MIN NOMUnit Operation Test MIN MAX Unit Conditions Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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