Texas Instruments
TSB12LV26
manual
Electrical Characteristics
±1. TSB12LV26 Block Diagram
Isochronous cycle timer
PCI Configuration Registers
Access TAG Name Meaning
Command Register
±3. Power Supply Terminals
CycleMatchEnable
Features
Page 20
2±8
Page 19
Page 21
Image 20
Page 19
Page 21
Contents
Data Manual
SLLS366A
TSB12LV26
Important Notice
Contents
Page
Mechanical Information
List of Illustrations
List of Tables
Vii
Viii
Features
Description
Related Documents
Ordering Information
Ordering Number Name Voltage Package
OHCI-Lynx PCI-Based Ieee 1394 Host Controller
PZ Package TOP View
Vccp Pciclkrun Pciinta 3.3 VCC
Vccp
CCP
±1. Signals Sorted by Terminal Number
Terminal Name
Terminal Description Name
±2. Signal Names Sorted Alphanumerically to Terminal Number
±3. Power Supply Terminals
±4. PCI System Terminals
PCIRST, terminal
Pciclk
As open-drain
During the data phase, AD31±AD0 contain data
±5. PCI Address and Data Terminals
±6. PCI Interface Control Terminals
Pcic BE0
Irdy
Pcitrdy
±7. Ieee 1394 PHY/Link Terminals
±8. Miscellaneous Terminals
Page
±1. Bit Field Access Tag Descriptions
Access TAG Name Meaning
±1. TSB12LV26 Block Diagram
PCI Configuration Registers
±2. PCI Configuration Register Map
Vendor ID Register
Register Name Offset
Command Register
Command
±3. Command Register Description
Device ID Register
±4. Status Register Description
Status Register
Status
Latency Timer and Class Cache Line Size Register
Latency timer and class cache line size
Class Code and Revision ID Register
Class code and revision ID
Header Type and Bist Register
Ohci Base Address Register
TI Extension Base Address Register
Subsystem Identification Register
TI extension base address
Subsystem identification
Power Management Capabilities Pointer Register
Register Power management capabilities pointer
Interrupt Line and Pin Register
Register Interrupt line and pin
Mingnt and Maxlat Register
Ohci Control Register
Capability ID and Next Item Pointer Register
Register Capability ID and next item pointer
Nextitem
Capabilityid
±14. Power Management Capabilities Register Description
Power Management Capabilities Register
Register Power management capabilities
Power Management Control and Status Register
Power Management Extension Register
Power management control and status
Power management extension
±17. Miscellaneous Configuration Register
Miscellaneous Configuration Register
Miscellaneous configuration
±18. Link Enhancement Control Register Description
Link Enhancement Control Register
Link enhancement control
Subsystem Access Register
Subsystem access
±19. Subsystem Access Register Description
Subdevid
±20. Gpio Control Register Description
Gpio Control Register
Gpio control
±18
Guid ROM Guidrom
±1. Ohci Register Map
DMA Context Register Name Abbreviation Offset
IsoRecvIntEventClear
Isochronous receive interrupt mask IsoRecvIntMaskSet
PhysicalRequestFilterHiClear
Physical request filter low PhysicalRequestFilterLoSet
Isochronous transmit context command
Isochronous receive context command
CommandPtr 40Ch + 32*n Pointer Context match ContextMatch
Asynchronous context control ContextControlSet
±2. Ohci Version Register Description
Ohci Version Register
Ohci version
Guid ROM Register
±3. Guid ROM Register Description
Guid ROM
RSU
Asynchronous Transmit Retries Register
CSR Data Register
Asynchronous transmit retries
±4. Asynchronous Transmit Retries Register Description
CSR Compare Register
CSR Control Register
CSR compare
CSR control
Configuration ROM Header Register
Configuration ROM header
±6. Configuration ROM Header Register Description
Bus Identification Register
±7. Bus Options Register Description
Bus Options Register
Bus options
Guid High Register
Guid Low Register
Guid high
Guid low
Configuration ROM Mapping Register
Configuration ROM mapping
±8. Configuration ROM Mapping Register Description
Posted Write Address Low Register
Posted Write Address High Register
Posted write address high
±9. Posted Write Address High Register Description
Vendor ID
±10. Host Controller Control Register Description
Host Controller Control Register
Host controller control
Self-ID Buffer Pointer Register
Self-ID Count Register
Self ID-buffer pointer
Self-ID count
Isochronous Receive Channel Mask High Register
Isochronous receive channel mask high
Isochronous Receive Channel Mask Low Register
Isochronous receive channel mask low
±14. Interrupt Event Register Description
Interrupt Event Register
Interrupt event
Arrs Rscu
Arrq Rscu
Interrupt Mask Register
Interrupt mask
±15. Interrupt Mask Register Description
Rscu RSC
Isochronous Transmit Interrupt Event Register
Isochronous transmit interrupt event
Isochronous Transmit Interrupt Mask Register
Isochronous transmit interrupt mask
±21
Isochronous transmit interrupt mask
Isochronous Receive Interrupt Event Register
Isochronous Receive Interrupt Mask Register
Isochronous receive interrupt event
Isochronous receive interrupt mask
Fairness Control Register
Fairness control
±18. Fairness Control Register Description
Fairness control
±19. Link Control Register Description
Link Control Register
Link control
Node Identification Register
Node identification
±20. Node Identification Register Description
CPS
±21. PHY Control Register Description
PHY Layer Control Register
PHY layer control
Isochronous Cycle Timer Register
Isochronous cycle timer
±22. Isochronous Cycle Timer Register Description
24±12
±23. Asynchronous Request Filter High Register Description
Asynchronous Request Filter High Register
Asynchronous request filter high
±29
Asynchronous Request Filter Low Register
Asynchronous request filter low
±24. Asynchronous Request Filter Low Register Description
±30
Physical Request Filter High Register
Physical request filter high
±25. Physical Request Filter High Register Description
Are accepted
±32
Physical Request Filter Low Register
Physical request filter low
±26. Physical Request Filter Low Register Description
Physical request filter low
Physical Upper Bound Register Optional Register
Physical upper bound
Physical upper bound
±34
Asynchronous Context Control Register
Asynchronous context control
±27. Asynchronous Context Control Register Description
Rscu RSU
31±4 DescriptorAddress
Asynchronous Context Command Pointer Register
Asynchronous context command pointer
RSC RSU
Isochronous Transmit Context Control Register
Isochronous transmit context control
Isochronous Transmit Context Command Pointer Register
Isochronous transmit context command pointer
Isochronous Receive Context Control Register
Isochronous receive context control
CycleMatchEnable
Reserved. Bits 27±16 return 0s when read
MultiChanMode
Match register see .43 is ignored
Isochronous Receive Context Command Pointer Register
Isochronous receive context command pointer
Isochronous receive context command pointer
±40
When the command descriptor w field is set to 11b
Isochronous Receive Context Match Register
Isochronous receive context match
±31. Isochronous Receive Context Match Register Description
±42
Gpio Interface
Page
13h PCI register 40h PCI Ohci register
±1. Registers and Bits Loadable through Serial ROM
ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM
Rsvd PME
±2. Serial ROM Map
Byte Byte Description Address
Electrical Characteristics
Absolute Maximum Ratings Over Operating Temperature Ranges²
Unit
Recommended Operating Conditions
Operation MIN NOM
Switching Characteristics for PCI Interface§
Switching Characteristics for PHY-Link Interface§
Operation Test MIN MAX Unit Conditions
Parameter Measured MIN TYP MAX Unit
Page
Mechanical Information
PZ S-PQFP-G100
Page
Important Notice
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