4.38 Asynchronous Context Command Pointer Register
The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables the context by setting the asynchronous context control register (see Section 4.37) bit 15 (run). See Table 4±28 for a complete description of the register contents.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| Asynchronous context command pointer |
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Type | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU |
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Default | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Bit | 15 |
| 14 |
| 13 |
| 12 | 11 |
| 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
Name |
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| Asynchronous context command pointer |
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Type | RWU |
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| RWU |
| RWU |
| RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | RWU | |
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Default | X |
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| X |
| X |
| X | X | X | X | X | X | X | X | X | X | X | |
| Register: | Asynchronous context command pointer |
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| Read/Write/Update |
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| Offset: |
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| 18Ch | [ATRQ] |
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| 1ACh | [ATRS] |
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| 1CCh | [ArRQ] |
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| 1ECh | [ArRS] |
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| Default: | XXXX XXXXh |
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| Table 4±28. Asynchronous Context Command Pointer Register Description |
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BIT | FIELD NAME |
| TYPE |
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| DESCRIPTION |
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31±4 | descriptorAddress | RWU | Contains the upper 28 bits of the address of a |
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3±0 |
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| Z |
| RWU | Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If | ||||||||||||||||
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| Z is 0, then it indicates that the descriptorAddress field (bits 31±4) is not valid. |
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4±36