Texas Instruments TSB12LV26 ±4. PCI System Terminals, PCIRST, terminal, Pciclk, As open-drain

Page 16

 

 

 

 

 

 

 

 

Table 2±4. PCI System Terminals

 

TERMINAL

 

I/O

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

NAME

 

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Global power reset. This reset brings all of the TSB12LV26 internal registers to their default states, including

 

 

 

 

 

 

 

 

those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional.

 

 

 

 

 

 

 

 

When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets

 

G_RST

 

10

I

 

 

 

 

 

 

to the TSB12LV26. G_RST should be a one-time power-on reset, and PCI_RST should be connected to the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus RST. If wake capabilities are not required, G_RST may be connected to the PCI bus RST (see

 

 

 

 

 

 

 

 

PCI_RST, terminal 76).

 

 

 

 

 

 

 

 

 

 

PCI_CLK

 

12

I

PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge

 

 

of PCI_CLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt signal. This output indicates interrupts from the TSB12LV26 to the host. This terminal is implemented

 

PCI_INTA

 

8

O

 

 

as open-drain.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI reset. When this bus reset is asserted, the TSB12LV26 places all output buffers in a high impedance state

 

 

 

 

 

 

 

 

and resets all internal registers except device power management context- and vendor-specific bits initialized

 

 

 

 

 

 

 

 

by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional.

 

PCI_RST

 

76

I

 

 

If this terminal is implemented, then it should be connected to the PCI bus RST signal. Otherwise, it should

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

be pulled high to link VCC through a 4.7-kΩresistor, or strapped to the G_RST terminal (see G_RST, terminal

 

 

 

 

 

 

 

 

10).

 

 

2±4

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables ViiViii Features DescriptionRelated Documents Ordering InformationOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerPZ Package TOP View Vccp Pciclkrun Pciinta 3.3 VCCVccp CCP±1. Signals Sorted by Terminal Number Terminal Name±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name ±4. PCI System Terminals PCIRST, terminalPciclk As open-drainDuring the data phase, AD31±AD0 contain data ±5. PCI Address and Data Terminals±6. PCI Interface Control Terminals Pcic BE0Irdy Pcitrdy±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning±1. TSB12LV26 Block Diagram PCI Configuration Registers ±2. PCI Configuration Register MapVendor ID Register Register Name OffsetCommand Register Command±3. Command Register Description Device ID RegisterStatus Status Register±4. Status Register Description Latency Timer and Class Cache Line Size Register Latency timer and class cache line sizeClass Code and Revision ID Register Class code and revision IDHeader Type and Bist Register Ohci Base Address RegisterTI Extension Base Address Register Subsystem Identification RegisterTI extension base address Subsystem identificationPower Management Capabilities Pointer Register Register Power management capabilities pointerInterrupt Line and Pin Register Register Interrupt line and pinMingnt and Maxlat Register Ohci Control RegisterCapability ID and Next Item Pointer Register Register Capability ID and next item pointerNextitem CapabilityidRegister Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power Management Control and Status Register Power Management Extension RegisterPower management control and status Power management extensionMiscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description Subsystem Access Register Subsystem access±19. Subsystem Access Register Description SubdevidGpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom IsoRecvIntEventClear Isochronous receive interrupt mask IsoRecvIntMaskSetPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous transmit context command Isochronous receive context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSetOhci version Ohci Version Register±2. Ohci Version Register Description Guid ROM Register ±3. Guid ROM Register DescriptionGuid ROM RSUAsynchronous Transmit Retries Register CSR Data RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Compare Register CSR Control RegisterCSR compare CSR controlConfiguration ROM Header Register Configuration ROM header±6. Configuration ROM Header Register Description Bus Identification RegisterBus options Bus Options Register±7. Bus Options Register Description Guid High Register Guid Low RegisterGuid high Guid lowConfiguration ROM Mapping Register Configuration ROM mapping±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted Write Address High Register Posted write address high±9. Posted Write Address High Register Description Vendor IDHost controller control Host Controller Control Register±10. Host Controller Control Register Description Self-ID Buffer Pointer Register Self-ID Count RegisterSelf ID-buffer pointer Self-ID countIsochronous Receive Channel Mask High Register Isochronous receive channel mask highIsochronous Receive Channel Mask Low Register Isochronous receive channel mask lowInterrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrs Rscu Arrq RscuInterrupt Mask Register Interrupt mask±15. Interrupt Mask Register Description Rscu RSCIsochronous Transmit Interrupt Event Register Isochronous transmit interrupt eventIsochronous Transmit Interrupt Mask Register Isochronous transmit interrupt mask±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Event Register Isochronous Receive Interrupt Mask RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness Control Register Fairness control±18. Fairness Control Register Description Fairness controlLink control Link Control Register±19. Link Control Register Description Node Identification Register Node identification±20. Node Identification Register Description CPSPHY layer control PHY Layer Control Register±21. PHY Control Register Description Isochronous Cycle Timer Register Isochronous cycle timer±22. Isochronous Cycle Timer Register Description 24±12Asynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 Asynchronous Request Filter Low Register Asynchronous request filter low±24. Asynchronous Request Filter Low Register Description ±30Physical Request Filter High Register Physical request filter high±25. Physical Request Filter High Register Description Are accepted±32 Physical Request Filter Low Register Physical request filter low±26. Physical Request Filter Low Register Description Physical request filter lowPhysical Upper Bound Register Optional Register Physical upper boundPhysical upper bound ±34Asynchronous Context Control Register Asynchronous context control±27. Asynchronous Context Control Register Description Rscu RSUAsynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous Transmit Context Command Pointer Register Isochronous transmit context command pointerIsochronous Receive Context Control Register Isochronous receive context controlCycleMatchEnable Reserved. Bits 27±16 return 0s when readMultiChanMode Match register see .43 is ignoredIsochronous Receive Context Command Pointer Register Isochronous receive context command pointerIsochronous receive context command pointer ±40When the command descriptor w field is set to 11b Isochronous Receive Context Match RegisterIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges²Operation MIN NOM Recommended Operating ConditionsUnit Switching Characteristics for PCI Interface§ Switching Characteristics for PHY-Link Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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