Texas Instruments TSB12LV26 manual Gpio Control Register, Gpio control

Page 37

3.23 GPIO Control Register

The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3±20 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

GPIO control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R/W

R

R/W

R/W

R

R

R

RWU

R/W

R

R/W

R/W

R

R

R

RWU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

 

14

13

12

 

11

10

9

8

7

6

5

4

3

2

1

0

Name

 

 

 

 

 

 

 

 

 

GPIO control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

R

 

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

0

 

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

GPIO control

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write/Update, ReadWrite, Read-only

 

 

 

 

 

 

 

 

Offset:

 

FCh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000 0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3±20. GPIO Control Register Description

BIT

FIELD NAME

TYPE

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

When this bit is set, a TSB12LV26 general-purpose interrupt event occurs on a level change of the

31

INT_3EN

R/W

 

GPIO3 input. This event may generate an interrupt, with mask and event status reported through the

 

OHCI interrupt mask (OHCI offset 88h/8Ch, see Section 4.22) and interrupt event (OHCI offset

 

 

 

 

 

 

 

 

80h/84h, see Section 4.21) registers.

 

 

 

 

 

30

RSVD

R

 

Reserved. Bit 30 returns 0 when read.

 

 

 

 

 

29

GPIO_INV3

R/W

 

GPIO3 polarity invert. When this bit is set, the polarity of GPIO3 is inverted.

 

 

 

 

 

28

GPIO_ENB3

R/W

 

GPIO3 enable control. When this bit is set, the output is enabled. Otherwise, the output is high

 

impedance.

 

 

 

 

 

 

 

 

 

27±25

RSVD

R

 

Reserved. Bits 27±25 return 0s when read.

 

 

 

 

 

24

GPIO_DATA3

RWU

 

GPIO3 data. Reads from this bit return the logical value of the input to GPIO3. Writes to this bit update

 

the value to drive to GPIO3 when output is enabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

When this bit is set, a TSB12LV26 general-purpose interrupt event occurs on a level change of the

23

INT_2EN

R/W

 

GPIO2 input. This event may generate an interrupt, with mask and event status reported through the

 

OHCI interrupt mask (OHCI offset 88h/8Ch, see Section 4.22) and interrupt event (OHCI offset

 

 

 

 

 

 

 

 

80h/84h, see Section 4.21) registers.

 

 

 

 

 

22

RSVD

R

 

Reserved. Bit 22 returns 0 when read.

 

 

 

 

 

21

GPIO_INV2

R/W

 

GPIO2 polarity invert. When this bit is set, the polarity of GPIO2 is inverted.

 

 

 

 

 

20

GPIO_ENB2

R/W

 

GPIO2 enable control. When this bit is set, the output is enabled. Otherwise, the output is high

 

impedance.

 

 

 

 

 

 

 

 

 

19±17

RSVD

R

 

Reserved. Bits 19±17 return 0s when read.

 

 

 

 

 

16

GPIO_DATA2

RWU

 

GPIO2 data. Reads from this bit return the logical value of the input to GPIO2. Writes to this bit update

 

the value to drive to GPIO2 when the output is enabled.

 

 

 

 

 

 

 

 

 

15±0

RSVD

R

 

Reserved. Bits 15±0 return 0s when read.

 

 

 

 

 

3±17

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Page 36 Page 38
Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOrdering Information Related DocumentsOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp Pciclkrun Pciinta 3.3 VCC PZ Package TOP ViewVccp CCPTerminal Name ±1. Signals Sorted by Terminal Number±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name PCIRST, terminal ±4. PCI System TerminalsPciclk As open-drain±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcic BE0 ±6. PCI Interface Control TerminalsIrdy Pcitrdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram ±2. PCI Configuration Register Map PCI Configuration RegistersVendor ID Register Register Name OffsetCommand Command Register±3. Command Register Description Device ID RegisterStatus Status Register±4. Status Register Description Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision IDOhci Base Address Register Header Type and Bist RegisterSubsystem Identification Register TI Extension Base Address RegisterTI extension base address Subsystem identificationRegister Power management capabilities pointer Power Management Capabilities Pointer RegisterInterrupt Line and Pin Register Register Interrupt line and pinOhci Control Register Mingnt and Maxlat RegisterRegister Capability ID and next item pointer Capability ID and Next Item Pointer RegisterNextitem CapabilityidRegister Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power Management Extension Register Power Management Control and Status RegisterPower management control and status Power management extensionMiscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description Subsystem access Subsystem Access Register±19. Subsystem Access Register Description SubdevidGpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous receive context command Isochronous transmit context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSetOhci version Ohci Version Register±2. Ohci Version Register Description ±3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSUCSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Control Register CSR Compare RegisterCSR compare CSR controlConfiguration ROM header Configuration ROM Header Register±6. Configuration ROM Header Register Description Bus Identification RegisterBus options Bus Options Register±7. Bus Options Register Description Guid Low Register Guid High RegisterGuid high Guid lowConfiguration ROM mapping Configuration ROM Mapping Register±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted write address high Posted Write Address High Register±9. Posted Write Address High Register Description Vendor IDHost controller control Host Controller Control Register±10. Host Controller Control Register Description Self-ID Count Register Self-ID Buffer Pointer RegisterSelf ID-buffer pointer Self-ID countIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrq Rscu Arrs RscuInterrupt mask Interrupt Mask Register±15. Interrupt Mask Register Description Rscu RSCIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Mask Register Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness control Fairness Control Register±18. Fairness Control Register Description Fairness controlLink control Link Control Register±19. Link Control Register Description Node identification Node Identification Register±20. Node Identification Register Description CPSPHY layer control PHY Layer Control Register±21. PHY Control Register Description Isochronous cycle timer Isochronous Cycle Timer Register±22. Isochronous Cycle Timer Register Description 24±12Asynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 Asynchronous request filter low Asynchronous Request Filter Low Register±24. Asynchronous Request Filter Low Register Description ±30Physical request filter high Physical Request Filter High Register±25. Physical Request Filter High Register Description Are accepted±32 Physical request filter low Physical Request Filter Low Register±26. Physical Request Filter Low Register Description Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34Asynchronous context control Asynchronous Context Control Register±27. Asynchronous Context Control Register Description Rscu RSUAsynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context controlReserved. Bits 27±16 return 0s when read CycleMatchEnableMultiChanMode Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous Receive Context Match Register When the command descriptor w field is set to 11bIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsOperation MIN NOM Recommended Operating ConditionsUnit Switching Characteristics for PHY-Link Interface§ Switching Characteristics for PCI Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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