Texas Instruments TSB12LV26 manual Power Management Capabilities Register

Page 32

3.17 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the TSB12LV26 related to PCI power management. See Table 3±14 for a complete description of the register contents.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Power management capabilities

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RU

RU

RU

RU

RU

RU

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

1

1

0

0

1

0

0

0

0

0

0

0

0

0

1

Register: Power management capabilities

Type: Read/Update, Read-only

Offset: 46h

Default: 6401h

Table 3±14. Power Management Capabilities Register Description

BIT

FIELD NAME

TYPE

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

support from D3cold. When this bit is set, the TSB12LV26 generates a

 

wake event

 

 

 

 

 

PCI_PME

 

PCI_PME

15

PME_D3COLD

RU

 

from D3cold. This bit state is dependent upon the TSB12LV26 VAUX implementation and may be

 

configured by host software using bit 15 (PME_D3COLD) in the PCI miscellaneous configuration

 

 

 

 

 

 

 

 

register (see Section 3.20).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

support. This 4-bit field indicates the power states from which the TSB12LV26 may assert

 

 

 

 

PCI_PME

14±11

PME_SUPPORT

RU

 

PCI_PME. This field returns a value of 1100b by default, indicating that PCI_PME may be asserted

 

from the D3hot and D2 power states. Bit 13 may be modified by host software using bit 13

 

 

 

 

 

 

 

 

(PME_SUPPORT_D2) in the PCI miscellaneous configuration register (offset F0h, see Section 3.20).

 

 

 

 

 

 

 

 

 

 

 

 

D2 support. This bit can be set or cleared via bit 10 (D2_SUPPORT) in the PCI miscellaneous

 

 

 

 

configuration register (see Section 3.20). The PCI miscellaneous configuration register is loaded from

10

D2_SUPPORT

RU

 

ROM. When this bit is set, it indicates that D2 support is present. When this bit is cleared, it indicates

 

 

 

 

that D2 support is not present for backward compatibility with the TSB12LV22. For normal operation,

 

 

 

 

this bit is set to 1.

 

 

 

 

 

 

 

 

9

D1_SUPPORT

R

 

D1 support. This bit returns a 0 when read, indicating that the TSB12LV26 does not support the D1

 

power state.

 

 

 

 

 

 

 

 

 

 

 

 

8

DYN_DATA

R

 

Dynamic data support. This bit returns a 0 when read, indicating that the TSB12LV26 does not report

 

dynamic power consumption data.

 

 

 

 

 

 

 

 

 

 

 

 

7±6

RSVD

R

 

Reserved. Bits 7±6 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

Device specific initialization. This bit returns 0 when read, indicating that the TSB12LV26 does not

5

DSI

R

 

require special initialization beyond the standard PCI configuration header before a generic class

 

 

 

 

driver is able to use it.

 

 

 

 

 

 

 

 

 

 

Auxiliary power source. Since the TSB12LV26 does not support

 

generation in the D3cold

4

AUX_PWR

R

 

PCI_PME

 

device state, this bit returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clock. This bit returns 0 when read, indicating that no host bus clock is required for the

3

PME_CLK

R

 

PME

 

TSB12LV26 to generate PCI_PME.

 

 

 

 

 

 

 

 

 

 

 

 

 

Power management version. This field returns 001b when read, indicating that the TSB12LV26 is

2±0

PM_VERSION

R

 

compatible with the registers described in the PCI Bus Power Management Interface Specification

 

 

 

 

Rev. 1.0.

3±12

Page 31 Page 33
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Page 31 Page 33
Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables ViiViii Features DescriptionRelated Documents Ordering InformationOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerPZ Package TOP View Vccp Pciclkrun Pciinta 3.3 VCCVccp CCP±1. Signals Sorted by Terminal Number Terminal NameTerminal Description Name ±2. Signal Names Sorted Alphanumerically to Terminal Number±3. Power Supply Terminals ±4. PCI System Terminals PCIRST, terminalPciclk As open-drainDuring the data phase, AD31±AD0 contain data ±5. PCI Address and Data Terminals±6. PCI Interface Control Terminals Pcic BE0Irdy Pcitrdy±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning±1. TSB12LV26 Block Diagram PCI Configuration Registers ±2. PCI Configuration Register MapVendor ID Register Register Name OffsetCommand Register Command±3. Command Register Description Device ID Register±4. Status Register Description Status RegisterStatus Latency Timer and Class Cache Line Size Register Latency timer and class cache line sizeClass Code and Revision ID Register Class code and revision IDHeader Type and Bist Register Ohci Base Address RegisterTI Extension Base Address Register Subsystem Identification RegisterTI extension base address Subsystem identificationPower Management Capabilities Pointer Register Register Power management capabilities pointerInterrupt Line and Pin Register Register Interrupt line and pinMingnt and Maxlat Register Ohci Control RegisterCapability ID and Next Item Pointer Register Register Capability ID and next item pointerNextitem Capabilityid±14. Power Management Capabilities Register Description Power Management Capabilities RegisterRegister Power management capabilities Power Management Control and Status Register Power Management Extension RegisterPower management control and status Power management extension±17. Miscellaneous Configuration Register Miscellaneous Configuration RegisterMiscellaneous configuration ±18. Link Enhancement Control Register Description Link Enhancement Control RegisterLink enhancement control Subsystem Access Register Subsystem access±19. Subsystem Access Register Description Subdevid±20. Gpio Control Register Description Gpio Control RegisterGpio control ±18 Guid ROM Guidrom ±1. Ohci Register MapDMA Context Register Name Abbreviation Offset IsoRecvIntEventClear Isochronous receive interrupt mask IsoRecvIntMaskSetPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous transmit context command Isochronous receive context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSet±2. Ohci Version Register Description Ohci Version RegisterOhci version Guid ROM Register ±3. Guid ROM Register DescriptionGuid ROM RSUAsynchronous Transmit Retries Register CSR Data RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Compare Register CSR Control RegisterCSR compare CSR controlConfiguration ROM Header Register Configuration ROM header±6. Configuration ROM Header Register Description Bus Identification Register±7. Bus Options Register Description Bus Options RegisterBus options Guid High Register Guid Low RegisterGuid high Guid lowConfiguration ROM Mapping Register Configuration ROM mapping±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted Write Address High Register Posted write address high±9. Posted Write Address High Register Description Vendor ID±10. Host Controller Control Register Description Host Controller Control RegisterHost controller control Self-ID Buffer Pointer Register Self-ID Count RegisterSelf ID-buffer pointer Self-ID countIsochronous Receive Channel Mask High Register Isochronous receive channel mask highIsochronous Receive Channel Mask Low Register Isochronous receive channel mask low±14. Interrupt Event Register Description Interrupt Event RegisterInterrupt event Arrs Rscu Arrq RscuInterrupt Mask Register Interrupt mask±15. Interrupt Mask Register Description Rscu RSCIsochronous Transmit Interrupt Event Register Isochronous transmit interrupt eventIsochronous Transmit Interrupt Mask Register Isochronous transmit interrupt mask±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Event Register Isochronous Receive Interrupt Mask RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness Control Register Fairness control±18. Fairness Control Register Description Fairness control±19. Link Control Register Description Link Control RegisterLink control Node Identification Register Node identification±20. Node Identification Register Description CPS±21. PHY Control Register Description PHY Layer Control RegisterPHY layer control Isochronous Cycle Timer Register Isochronous cycle timer±22. Isochronous Cycle Timer Register Description 24±12±23. Asynchronous Request Filter High Register Description Asynchronous Request Filter High RegisterAsynchronous request filter high ±29 Asynchronous Request Filter Low Register Asynchronous request filter low±24. Asynchronous Request Filter Low Register Description ±30Physical Request Filter High Register Physical request filter high±25. Physical Request Filter High Register Description Are accepted±32 Physical Request Filter Low Register Physical request filter low±26. Physical Request Filter Low Register Description Physical request filter lowPhysical Upper Bound Register Optional Register Physical upper boundPhysical upper bound ±34Asynchronous Context Control Register Asynchronous context control±27. Asynchronous Context Control Register Description Rscu RSU31±4 DescriptorAddress Asynchronous Context Command Pointer RegisterAsynchronous context command pointer RSC RSU Isochronous Transmit Context Control RegisterIsochronous transmit context control Isochronous Transmit Context Command Pointer Register Isochronous transmit context command pointerIsochronous Receive Context Control Register Isochronous receive context controlCycleMatchEnable Reserved. Bits 27±16 return 0s when readMultiChanMode Match register see .43 is ignoredIsochronous Receive Context Command Pointer Register Isochronous receive context command pointerIsochronous receive context command pointer ±40When the command descriptor w field is set to 11b Isochronous Receive Context Match RegisterIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page 13h PCI register 40h PCI Ohci register ±1. Registers and Bits Loadable through Serial ROMROM Offset OHCI/PCI Offset Register Bits Loaded From ROM Rsvd PME ±2. Serial ROM MapByte Byte Description Address Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges²Unit Recommended Operating ConditionsOperation MIN NOM Switching Characteristics for PCI Interface§ Switching Characteristics for PHY-Link Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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