Texas Instruments TSB12LV26 manual Power Management Control and Status Register

Page 33

3.18 Power Management Control and Status Register

The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 3±15 for a complete description of the register contents.

Bit

15

 

14

13

 

12

 

 

11

 

10

9

8

7

 

6

 

5

4

 

3

 

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Power management control and status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RC

 

R

R

 

R

 

R

R

R

R/W

R

 

R

 

R

R

R

 

R

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

 

0

 

0

0

0

0

 

0

 

0

0

 

0

 

 

0

0

0

 

 

Register:

Power management control and status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Clear, Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

48h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3±15. Power Management Control and Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is set when the TSB12LV26 would normally be asserting the

 

signal, independent of the

 

 

 

 

 

 

 

 

 

 

PME

15

 

PME_STS

 

RC

 

 

state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, and this also clears the PCI_PME

 

 

 

 

 

 

 

 

 

 

signal driven by the TSB12LV26. Writing a 0 to this bit has no effect.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14±9

 

DYN_CTRL

 

R

 

 

Dynamic data control. This field returns 0s when read since the TSB12LV26 does not report dynamic

 

 

 

 

data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

enable. This bit enables the function to assert

 

 

If this bit is cleared, then assertion

8

 

PME_ENB

 

R/W

 

 

PCI_PME

PCI_PME.

 

 

 

 

of PCI_PME is disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7±5

 

RSVD

 

R

 

 

Reserved. Bits 7±5 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

DYN_DATA

 

R

 

 

Dynamic data. This bit returns 0 when read since the TSB12LV26 does not report dynamic data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±2

 

RSVD

 

R

 

 

Reserved. Bits 3±2 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power state. This 2-bit field is used to set the TSB12LV26 device power state and is encoded as

 

 

 

 

 

 

 

 

 

 

follows:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1±0

 

PWR_STATE

 

R/W

 

 

 

00 = Current power state is D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

01 = Current power state is D1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 = Current power state is D2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11 = Current power state is D3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.19 Power Management Extension Register

The power management extension register provides extended power management features not applicable to the TSB12LV26, thus it is read-only and returns 0s when read. See Table 3±16 for a complete description of the register contents.

Bit

15

 

14

13

 

12

 

 

11

10

9

 

8

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Power management extension

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

R

 

R

 

R

R

R

 

R

R

 

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

 

0

0

0

 

0

0

 

0

0

0

0

0

0

0

 

 

Register:

Power management extension

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

4Ah

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

 

0000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3±16. Power Management Extension Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15±8

 

PM_DATA

 

R

 

 

Power management data. This field returns 00h when read since the TSB12LV26 does not report

 

 

 

 

dynamic data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7±0

 

PMCSR_BSE

 

R

 

 

Power management CSR ± bridge support extensions. This field returns 00h when read since the

 

 

 

 

TSB12LV26 does not provide P2P bridging.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±13

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Page 32 Page 34
Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOrdering Information Related DocumentsOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp Pciclkrun Pciinta 3.3 VCC PZ Package TOP ViewVccp CCPTerminal Name ±1. Signals Sorted by Terminal Number±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name PCIRST, terminal ±4. PCI System TerminalsPciclk As open-drain±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcic BE0 ±6. PCI Interface Control TerminalsIrdy Pcitrdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram ±2. PCI Configuration Register Map PCI Configuration RegistersVendor ID Register Register Name OffsetCommand Command Register±3. Command Register Description Device ID RegisterStatus Register Status±4. Status Register Description Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision IDOhci Base Address Register Header Type and Bist RegisterSubsystem Identification Register TI Extension Base Address RegisterTI extension base address Subsystem identificationRegister Power management capabilities pointer Power Management Capabilities Pointer RegisterInterrupt Line and Pin Register Register Interrupt line and pinOhci Control Register Mingnt and Maxlat RegisterRegister Capability ID and next item pointer Capability ID and Next Item Pointer RegisterNextitem CapabilityidPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power Management Extension Register Power Management Control and Status RegisterPower management control and status Power management extensionMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description Subsystem access Subsystem Access Register±19. Subsystem Access Register Description SubdevidGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous receive context command Isochronous transmit context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSetOhci Version Register Ohci version±2. Ohci Version Register Description ±3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSUCSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Control Register CSR Compare RegisterCSR compare CSR controlConfiguration ROM header Configuration ROM Header Register±6. Configuration ROM Header Register Description Bus Identification RegisterBus Options Register Bus options±7. Bus Options Register Description Guid Low Register Guid High RegisterGuid high Guid lowConfiguration ROM mapping Configuration ROM Mapping Register±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted write address high Posted Write Address High Register±9. Posted Write Address High Register Description Vendor IDHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self-ID Count Register Self-ID Buffer Pointer RegisterSelf ID-buffer pointer Self-ID countIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrq Rscu Arrs RscuInterrupt mask Interrupt Mask Register±15. Interrupt Mask Register Description Rscu RSCIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Mask Register Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness control Fairness Control Register±18. Fairness Control Register Description Fairness controlLink Control Register Link control±19. Link Control Register Description Node identification Node Identification Register±20. Node Identification Register Description CPSPHY Layer Control Register PHY layer control±21. PHY Control Register Description Isochronous cycle timer Isochronous Cycle Timer Register±22. Isochronous Cycle Timer Register Description 24±12Asynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 Asynchronous request filter low Asynchronous Request Filter Low Register±24. Asynchronous Request Filter Low Register Description ±30Physical request filter high Physical Request Filter High Register±25. Physical Request Filter High Register Description Are accepted±32 Physical request filter low Physical Request Filter Low Register±26. Physical Request Filter Low Register Description Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34Asynchronous context control Asynchronous Context Control Register±27. Asynchronous Context Control Register Description Rscu RSUAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context controlReserved. Bits 27±16 return 0s when read CycleMatchEnableMultiChanMode Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous Receive Context Match Register When the command descriptor w field is set to 11bIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsRecommended Operating Conditions Operation MIN NOMUnit Switching Characteristics for PHY-Link Interface§ Switching Characteristics for PCI Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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