Texas Instruments TSB12LV26 manual Isochronous Transmit Context Control Register, Rsc Rsu

Page 75

4.39 Isochronous Transmit Context Control Register

The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,… , 7). See Table 4±29 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

 

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

Isochronous transmit context control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RSCU

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

RSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Bit

15

 

14

13

12

 

11

10

9

 

8

7

6

 

5

4

3

2

1

0

Name

 

 

 

 

 

 

 

 

Isochronous transmit context control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RSC

 

R

R

RSU

 

RU

RU

 

R

 

R

RU

RU

 

RU

RU

RU

RU

RU

RU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

X

 

0

0

 

0

 

0

X

X

 

X

X

X

X

X

X

 

Register:

Isochronous transmit context control

 

 

 

 

 

 

 

 

 

Type:

 

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

 

 

 

 

Offset:

 

200h + (16 * n)

set register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

204h + (16 * n)

clear register

 

 

 

 

 

 

 

 

 

 

 

Default:

 

XXXX X0XXh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4±29. Isochronous Transmit Context Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

 

 

 

 

 

 

 

When this bit is set to 1, processing occurs such that the packet described by the context first

 

 

 

descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field

 

 

 

(bits 30±16). The cycleMatch field (bits 30±16) must match the low-order two bits of cycleSeconds

 

 

 

and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before

31

cycleMatchEnable

RSCU

isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead,

the processing of the first descriptor block may begin slightly in advance of the actual cycle in which

 

 

 

 

 

 

the first packet is transmitted.

 

 

 

The effects of this bit, however, are impacted by the values of other bits in this register and are

 

 

 

explained in the 1394 Open Host Controller Interface Specification. Once the context has become

 

 

 

active, hardware clears this bit.

 

 

 

 

 

 

 

Contains a 15-bit value, corresponding to the low-order two bits of the bus isochronous cycle timer

 

 

 

register (OHCI offset F0h, see Section 4.31) cycleSeconds field (bits 31±25) and the cycleCount field

30±16

cycleMatch

RSC

(bits 24±12). If bit 31 (cycleMatchEnable) is set, then this isochronous transmit DMA context

becomes enabled for transmits when the low-order two bits of the bus isochronous cycle timer

 

 

 

 

 

 

register cycleSeconds field (bits 31±25) and the cycleCount field (bits 24±12) value equal this field

 

 

 

(cycleMatch) value.

 

 

 

 

15

run

RSC

This bit is set by software to enable descriptor processing for the context and cleared by software to

stop descriptor processing. The TSB12LV26 changes this bit only on a hardware or software reset.

 

 

 

 

 

 

 

14±13

RSVD

R

Reserved. Bits 14±13 return 0s when read.

 

 

 

 

12

wake

RSU

Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The

TSB12LV26 clears this bit on every descriptor fetch.

 

 

 

 

 

 

 

11

dead

RU

The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets

bit 15 (run).

 

 

 

 

 

 

 

10

active

RU

The TSB12LV26 sets this bit to 1 when it is processing descriptors.

 

 

 

 

9±8

RSVD

R

Reserved. Bits 9±8 return 0s when read.

 

 

 

 

7±5

spd

RU

This field is not meaningful for isochronous transmit contexts.

 

 

 

 

4±0

event code

RU

Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are:

ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.

 

 

 

 

 

 

 

4±37

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Contents
Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage PackageCCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC VccpTerminal Name ±1. Signals Sorted by Terminal Number±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers±2. PCI Configuration Register Map Vendor ID RegisterDevice ID Register Command RegisterCommand ±3. Command Register DescriptionStatus Register Status±4. Status Register Description Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID RegisterOhci Base Address Register Header Type and Bist RegisterSubsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base addressRegister Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin RegisterOhci Control Register Mingnt and Maxlat RegisterCapabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer NextitemPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and statusMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register DescriptionGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClearAsynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatchOhci Version Register Ohci version±2. Ohci Version Register Description RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retriesCSR control CSR Compare RegisterCSR Control Register CSR compareBus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register DescriptionBus Options Register Bus options±7. Bus Options Register Description Guid low Guid High RegisterGuid Low Register Guid highPosted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register DescriptionVendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register DescriptionHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointerIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrq Rscu Arrs RscuRscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register DescriptionIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt eventFairness control Fairness Control RegisterFairness control ±18. Fairness Control Register DescriptionLink Control Register Link control±19. Link Control Register Description CPS Node Identification RegisterNode identification ±20. Node Identification Register DescriptionPHY Layer Control Register PHY layer control±21. PHY Control Register Description 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register DescriptionAsynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register DescriptionAre accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description±32 Physical request filter low Physical Request Filter Low Register Physical request filter low ±26. Physical Request Filter Low Register Description±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper boundRscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register DescriptionAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control RegisterMatch register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsRecommended Operating Conditions Operation MIN NOMUnit Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice
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