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4.39 Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,… , 7). See Table 4±29 for a complete description of the register contents.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 |
| 21 | 20 | 19 | 18 | 17 | 16 |
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Name |
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| Isochronous transmit context control |
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Type | RSCU | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | RSC | |
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Default | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
Bit | 15 |
| 14 | 13 | 12 |
| 11 | 10 | 9 |
| 8 | 7 | 6 |
| 5 | 4 | 3 | 2 | 1 | 0 | |
Name |
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| Isochronous transmit context control |
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Type | RSC |
| R | R | RSU |
| RU | RU |
| R |
| R | RU | RU |
| RU | RU | RU | RU | RU | RU |
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Default | 0 |
| 0 | 0 | X |
| 0 | 0 |
| 0 |
| 0 | X | X |
| X | X | X | X | X | X |
| Register: | Isochronous transmit context control |
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| Type: |
| Read/Set/Clear/Update, Read/Set/Clear, Read/Update, |
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| Offset: |
| 200h + (16 * n) | set register |
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| 204h + (16 * n) | clear register |
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| Default: |
| XXXX X0XXh |
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Table 4±29. Isochronous Transmit Context Control Register Description
BIT | FIELD NAME | TYPE | DESCRIPTION | |
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| When this bit is set to 1, processing occurs such that the packet described by the context first | |
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| descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field | |
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| (bits 30±16). The cycleMatch field (bits 30±16) must match the | |
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| and the | |
31 | cycleMatchEnable | RSCU | isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead, | |
the processing of the first descriptor block may begin slightly in advance of the actual cycle in which | ||||
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| the first packet is transmitted. | |
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| The effects of this bit, however, are impacted by the values of other bits in this register and are | |
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| explained in the 1394 Open Host Controller Interface Specification. Once the context has become | |
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| active, hardware clears this bit. | |
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| Contains a | |
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| register (OHCI offset F0h, see Section 4.31) cycleSeconds field (bits 31±25) and the cycleCount field | |
30±16 | cycleMatch | RSC | (bits 24±12). If bit 31 (cycleMatchEnable) is set, then this isochronous transmit DMA context | |
becomes enabled for transmits when the | ||||
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| register cycleSeconds field (bits 31±25) and the cycleCount field (bits 24±12) value equal this field | |
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| (cycleMatch) value. | |
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15 | run | RSC | This bit is set by software to enable descriptor processing for the context and cleared by software to | |
stop descriptor processing. The TSB12LV26 changes this bit only on a hardware or software reset. | ||||
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14±13 | RSVD | R | Reserved. Bits 14±13 return 0s when read. | |
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12 | wake | RSU | Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The | |
TSB12LV26 clears this bit on every descriptor fetch. | ||||
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11 | dead | RU | The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets | |
bit 15 (run). | ||||
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10 | active | RU | The TSB12LV26 sets this bit to 1 when it is processing descriptors. | |
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9±8 | RSVD | R | Reserved. Bits 9±8 return 0s when read. | |
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7±5 | spd | RU | This field is not meaningful for isochronous transmit contexts. | |
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4±0 | event code | RU | Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are: | |
ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown. | ||||
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4±37