Texas Instruments TSB12LV26 manual ±4. Status Register Description

Page 25

3.5 Status Register

The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 3±4 for a complete description of the register contents.

Bit

15

 

14

13

 

12

 

11

10

 

9

8

 

7

 

6

5

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

RCU

 

RCU

RCU

 

RCU

RCU

R

 

R

RCU

 

R

 

R

 

R

 

R

 

R

 

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

0

 

0

 

0

0

 

1

0

 

0

 

0

0

1

 

0

 

0

 

0

0

 

 

Register:

Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Clear/Update, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

 

06h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0210h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3±4. Status Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

 

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

PAR_ERR

 

RCU

Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signaled system error. This bit is set when

 

 

 

 

is enabled and the TSB12LV26 has signaled a

14

 

SYS_ERR

 

RCU

PCI_SERR

 

 

system error to the host.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

MABORT

 

RCU

Received master abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus has been

 

 

terminated by a master abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

TABORT_REC

 

RCU

Received target abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus was

 

 

terminated by a target abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

TABORT_SIG

 

RCU

Signaled target abort. This bit is set by the TSB12LV26 when it terminates a transaction on the PCI bus

 

 

with a target abort.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEVSEL timing. Bits 10±9 encode the timing of

 

 

 

 

and are hardwired to 01b indicating that

10±9

 

PCI_SPEED

 

R

 

PCI_DEVSEL

 

 

 

the TSB12LV26 asserts this signal at a medium speed on nonconfiguration cycle accesses.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data parity error detected. This bit is set when the following conditions have been met:

 

 

8

 

DATAPAR

 

RCU

 

a. PCI_PERR was asserted by any PCI device including the TSB12LV26.

 

 

 

 

 

 

 

b. The TSB12LV26 was the bus master during the data parity error.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c. The parity error response bit is set in the PCI command register (offset 04h, see Section 3.4).

 

 

 

 

 

 

 

 

 

 

7

 

FBB_CAP

 

R

 

Fast back-to-back capable. The TSB12LV26 cannot accept fast back-to-back transactions; thus, this

 

 

 

bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

UDF

 

 

R

 

User definable features (UDF) supported. The TSB12LV26 does not support the UDF; thus, this bit is

 

 

 

 

hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

66MHZ

 

 

R

 

66-MHz capable. The TSB12LV26 operates at a maximum PCI_CLK frequency of 33 MHz; therefore,

 

 

 

 

this bit is hardwired to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

CAPLIST

 

R

 

Capabilities list. This bit returns 1 when read, indicating that capabilities additional to standard PCI are

 

 

 

implemented. The linked list of PCI power management capabilities is implemented in this function.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±0

 

RSVD

 

 

R

 

Reserved. Bits 3±0 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±5

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOrdering Information Related DocumentsOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp Pciclkrun Pciinta 3.3 VCC PZ Package TOP ViewVccp CCPTerminal Name ±1. Signals Sorted by Terminal Number±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name PCIRST, terminal ±4. PCI System TerminalsPciclk As open-drain±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcic BE0 ±6. PCI Interface Control TerminalsIrdy Pcitrdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram ±2. PCI Configuration Register Map PCI Configuration RegistersVendor ID Register Register Name OffsetCommand Command Register±3. Command Register Description Device ID RegisterStatus Status Register±4. Status Register Description Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision IDOhci Base Address Register Header Type and Bist RegisterSubsystem Identification Register TI Extension Base Address RegisterTI extension base address Subsystem identificationRegister Power management capabilities pointer Power Management Capabilities Pointer RegisterInterrupt Line and Pin Register Register Interrupt line and pinOhci Control Register Mingnt and Maxlat RegisterRegister Capability ID and next item pointer Capability ID and Next Item Pointer RegisterNextitem CapabilityidRegister Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power Management Extension Register Power Management Control and Status RegisterPower management control and status Power management extensionMiscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description Subsystem access Subsystem Access Register±19. Subsystem Access Register Description SubdevidGpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous receive context command Isochronous transmit context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSetOhci version Ohci Version Register±2. Ohci Version Register Description ±3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSUCSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Control Register CSR Compare RegisterCSR compare CSR controlConfiguration ROM header Configuration ROM Header Register±6. Configuration ROM Header Register Description Bus Identification RegisterBus options Bus Options Register±7. Bus Options Register Description Guid Low Register Guid High RegisterGuid high Guid lowConfiguration ROM mapping Configuration ROM Mapping Register±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted write address high Posted Write Address High Register±9. Posted Write Address High Register Description Vendor IDHost controller control Host Controller Control Register±10. Host Controller Control Register Description Self-ID Count Register Self-ID Buffer Pointer RegisterSelf ID-buffer pointer Self-ID countIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrq Rscu Arrs RscuInterrupt mask Interrupt Mask Register±15. Interrupt Mask Register Description Rscu RSCIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Mask Register Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness control Fairness Control Register±18. Fairness Control Register Description Fairness controlLink control Link Control Register±19. Link Control Register Description Node identification Node Identification Register±20. Node Identification Register Description CPSPHY layer control PHY Layer Control Register±21. PHY Control Register Description Isochronous cycle timer Isochronous Cycle Timer Register±22. Isochronous Cycle Timer Register Description 24±12Asynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 Asynchronous request filter low Asynchronous Request Filter Low Register±24. Asynchronous Request Filter Low Register Description ±30Physical request filter high Physical Request Filter High Register±25. Physical Request Filter High Register Description Are accepted±32 Physical request filter low Physical Request Filter Low Register±26. Physical Request Filter Low Register Description Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34Asynchronous context control Asynchronous Context Control Register±27. Asynchronous Context Control Register Description Rscu RSUAsynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context controlReserved. Bits 27±16 return 0s when read CycleMatchEnableMultiChanMode Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous Receive Context Match Register When the command descriptor w field is set to 11bIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsOperation MIN NOM Recommended Operating ConditionsUnit Switching Characteristics for PHY-Link Interface§ Switching Characteristics for PCI Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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