Texas Instruments TSB12LV26 manual Interrupt Event Register, Interrupt event

Page 55

4.21 Interrupt Event Register

The interrupt event set/clear register reflects the state of the various TSB12LV26 interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.

This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1.0 compliant vendor-specific interrupt function to bit 30. When reading the interrupt event register, the return value is the bit-wise AND function of the interrupt event and interrupt mask registers per the 1394 Open Host Controller Interface Specification. See Table 4±14 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Interrupt event

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

RSC

R

R

R

RSCU

RSCU

RSCU

RSCU

RSCU

RSCU

RSCU

RSCU

R

RSCU

RSCU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

X

0

0

0

X

X

X

X

X

X

X

X

0

X

X

Bit

15

14

 

13

 

 

12

 

11

10

9

8

7

 

6

5

4

3

2

1

0

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt event

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

 

R

 

R

 

 

R

 

R

 

R

RSCU

RSCU

RU

 

RU

RSCU

RSCU

RSCU

RSCU

RSCU

RSCU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

 

0

 

0

 

 

0

 

0

 

0

X

X

X

 

X

X

X

X

X

X

X

 

Register:

Interrupt event

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

 

 

 

 

Offset:

80h

 

set register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

84h

 

clear register [returns the content of the interrupt event and interrupt mask registers

 

 

 

 

 

 

 

 

 

when read]

 

 

 

 

 

 

 

 

 

 

 

 

Default:

XXXX 0XXXh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4±14. Interrupt Event Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

RSVD

 

 

 

R

 

 

Reserved. Bit 31 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This vendor-specific interrupt event is reported when either of the general-purpose interrupts occur

30

vendorSpecific

 

RSC

 

 

which are enabled via INT3_EN and INT2_EN in the GPIO control register (offset FCh, see Section

 

 

 

 

 

 

 

 

 

 

 

 

3.23).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29±27

 

 

RSVD

 

 

 

R

 

 

Reserved. Bits 29±27 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

phyRegRcvd

 

RSCU

 

 

The TSB12LV26 has received a PHY register data byte which can be read from the PHY layer control

 

 

 

register (OHCI offset ECh, see Section 4.30).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If bit 21 (cycleMaster) of the link control register (OHCI offset E0h/E4h, see Section 4.28) is set, then

25

cycleTooLong

 

RSCU

 

 

this indicates that over 125 ∝s have elapsed between the start of sending a cycle start packet and the

 

 

 

 

 

 

 

 

 

 

 

 

end of a subaction gap. The link control register bit 21 (cycleMaster) is cleared by this event.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This event occurs when the TSB12LV26 encounters any error that forces it to stop operations on any

24

unrecoverableError

 

RSCU

 

 

or all of its subunits, for example, when a DMA context sets its dead bit. While this bit is set, all normal

 

 

 

 

 

 

 

 

 

 

 

 

interrupts for the context(s) that caused this interrupt are blocked from being set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A cycle start was received that had values for cycleSeconds and cycleCount fields that are different

23

cycleInconsistent

 

RSCU

 

 

from the values in bits 31±25 (cycleSeconds field) and bits 24±12 (cycleCount field) of the

 

 

 

 

 

 

 

 

 

 

 

 

isochronous cycle timer register (OHCI offset F0h, see Section 4.31).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A lost cycle is indicated when no cycle_start packet is sent/received between two successive

 

 

 

 

 

 

 

 

 

 

 

 

cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately

22

 

cycleLost

 

 

 

RSCU

 

 

follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after

 

 

 

 

 

 

 

 

 

 

 

 

a cycleSynch event without an intervening cycle start. This bit may be set either when a lost cycle

 

 

 

 

 

 

 

 

 

 

 

 

occurs or when logic predicts that one will occur.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

cycle64Seconds

 

RSCU

 

 

Indicates that the 7th bit of the cycle second counter has changed.

 

 

 

20

 

cycleSynch

 

RSCU

 

 

Indicates that a new isochronous cycle has started. This bit is set when the low order bit of the cycle

 

 

 

 

count toggles.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

 

phy

 

 

 

RSCU

 

 

Indicates that the PHY requests an interrupt through a status transfer.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

RSVD

 

 

 

R

 

 

Reserved. Bit 18 returns 0 when read.

 

 

 

 

 

 

 

4±17

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage PackageCCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC VccpTerminal Name ±1. Signals Sorted by Terminal Number±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers±2. PCI Configuration Register Map Vendor ID RegisterDevice ID Register Command RegisterCommand ±3. Command Register DescriptionStatus Status Register±4. Status Register Description Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID RegisterOhci Base Address Register Header Type and Bist RegisterSubsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base addressRegister Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin RegisterOhci Control Register Mingnt and Maxlat RegisterCapabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer NextitemRegister Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and statusMiscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register DescriptionGpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClearAsynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatchOhci version Ohci Version Register±2. Ohci Version Register Description RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retriesCSR control CSR Compare RegisterCSR Control Register CSR compareBus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register DescriptionBus options Bus Options Register±7. Bus Options Register Description Guid low Guid High RegisterGuid Low Register Guid highPosted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register DescriptionVendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register DescriptionHost controller control Host Controller Control Register±10. Host Controller Control Register Description Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointerIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrq Rscu Arrs RscuRscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register DescriptionIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt eventFairness control Fairness Control RegisterFairness control ±18. Fairness Control Register DescriptionLink control Link Control Register±19. Link Control Register Description CPS Node Identification RegisterNode identification ±20. Node Identification Register DescriptionPHY layer control PHY Layer Control Register±21. PHY Control Register Description 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register DescriptionAsynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register DescriptionAre accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description±32 Physical request filter low Physical Request Filter Low RegisterPhysical request filter low ±26. Physical Request Filter Low Register Description±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper boundRscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register DescriptionAsynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control RegisterMatch register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsOperation MIN NOM Recommended Operating ConditionsUnit Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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