Header Type and Bist Register | Texas Instruments TSB12LV26 specification

Texas Instruments TSB12LV26 manual Header Type and Bist Register, Ohci Base Address Register

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3.8 Header Type and BIST Register

The header type and BIST register indicates the TSB12LV26 PCI header type, and indicates no built-in self test. See Table 3±7 for a complete description of the register contents.

Bit	15	14	13	12	11	10	9		8	7	6	5	4	3	2	1	0

Name								Header type and BIST

Type	R	R	R	R	R	R	R		R	R	R	R	R	R	R	R	R

Default	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0

Type: Read-only

Offset: 0Eh

Default: 0000h

Table 3±7. Header Type and BIST Register Description

BIT	FIELD NAME	TYPE	DESCRIPTION

15±8	BIST	R	Built-in self test. The TSB12LV26 does not include a built-in self test; thus, this field returns 00h when
15±8	BIST	R	read.
			read.

7±0	HEADER_TYPE	R	PCI header type. The TSB12LV26 includes the standard PCI header, and this is communicated by
7±0	HEADER_TYPE	R	returning 00h when this field is read.
			returning 00h when this field is read.

3.9 OHCI Base Address Register

The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 3±8 for a complete description of the register contents.

Bit	31	30	29		28		27	26	25		24	23	22	21	20	19	18	17	16

Name										OHCI base address

Type	R/W	R/W	R/W		R/W		R/W	R/W	R/W		R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Default	0	0	0		0		0	0	0		0	0	0	0	0	0	0	0	0

Bit	15	14	13		12		11	10	9		8	7	6	5	4	3	2	1	0

Name											OHCI address

Type	R/W	R/W	R/W		R/W		R/W	R	R		R	R	R	R	R	R	R	R	R

Default	0	0	0		0		0	0	0		0	0	0	0	0	0	0	0	0

	Register:		OHCI base address
	Type:		Read/Write, Read-only
	Offset:		10h
	Default:		0000 0000h
					Table 3±8. OHCI Base Address Register Description

BIT	FIELD NAME			TYPE									DESCRIPTION

31±11	OHCIREG_PTR			R/W		OHCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI base address register.

10±4	OHCI_SZ				R	OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a
10±4	OHCI_SZ				R	2-Kbyte region of memory.
						2-Kbyte region of memory.

3	OHCI_PF				R	OHCI register prefetch. This bit returns 0 when read, indicating that the OHCI registers are
3	OHCI_PF				R	nonprefetchable.
						nonprefetchable.

2±1	OHCI_MEMTYPE				R	OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is
2±1	OHCI_MEMTYPE				R	32 bits wide and mapping can be done anywhere in the 32-bit memory space.


0	OHCI_MEM				R	OHCI memory indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped
0	OHCI_MEM				R	into system memory space.
						into system memory space.

3±7

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Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage PackageCCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC VccpTerminal Name ±1. Signals Sorted by Terminal Number±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers ±2. PCI Configuration Register Map Vendor ID RegisterDevice ID Register Command RegisterCommand ±3. Command Register DescriptionStatus Register Status±4. Status Register Description Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID RegisterOhci Base Address Register Header Type and Bist RegisterSubsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base addressRegister Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin RegisterOhci Control Register Mingnt and Maxlat RegisterCapabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer NextitemPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and statusMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register DescriptionGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClearAsynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatchOhci Version Register Ohci version±2. Ohci Version Register Description RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retriesCSR control CSR Compare RegisterCSR Control Register CSR compareBus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register DescriptionBus Options Register Bus options±7. Bus Options Register Description Guid low Guid High RegisterGuid Low Register Guid highPosted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register DescriptionVendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register DescriptionHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointerIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrq Rscu Arrs RscuRscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register DescriptionIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt eventFairness control Fairness Control RegisterFairness control ±18. Fairness Control Register DescriptionLink Control Register Link control±19. Link Control Register Description CPS Node Identification RegisterNode identification ±20. Node Identification Register DescriptionPHY Layer Control Register PHY layer control±21. PHY Control Register Description 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register DescriptionAsynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register DescriptionAre accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description±32 Physical request filter low Physical Request Filter Low RegisterPhysical request filter low ±26. Physical Request Filter Low Register Description±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper boundRscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register DescriptionAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control RegisterMatch register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsRecommended Operating Conditions Operation MIN NOMUnit Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

Texas Instruments TSB12LV26 manual Header Type and Bist Register, Ohci Base Address Register

3.8 Header Type and BIST Register

Table 3±7. Header Type and BIST Register Description

BIT

BIST

HEADER_TYPE

3.9 OHCI Base Address Register

Table 3±8. OHCI Base Address Register Description

BIT

OHCIREG_PTR

OHCI_SZ

OHCI_PF

OHCI_MEMTYPE

OHCI_MEM