Texas Instruments TSB12LV26 manual Bus Options Register, Bus options

Page 47

4.9 Bus Options Register

The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4±7 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Bus options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

X

X

X

X

0

0

0

0

X

X

X

X

X

X

X

X

Bit

15

14

13

12

 

11

 

10

 

9

8

 

7

 

6

5

4

3

2

 

1

0

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bus options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R/W

 

R/W

R/W

 

R/W

 

R

 

R

 

R

R

R/W

 

R/W

 

R

R

 

R

R

 

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

1

 

0

1

 

0

 

 

0

 

0

 

0

0

 

X

 

X

 

0

0

 

0

0

 

1

0

 

Register:

Bus options

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

20h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

X0XX A0X2h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4±7. Bus Options Register Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

FIELD NAME

 

TYPE

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

irmc

 

R/W

 

Isochronous resource manager capable. IEEE 1394 bus management field. Must be valid when bit 17

 

 

 

(linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

cmc

 

R/W

 

Cycle master capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the

 

 

 

host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

isc

 

R/W

 

Isochronous support

capable. IEEE

1394

bus

management

field. Must

be valid

when

bit 17

 

 

 

(linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

bmc

 

R/W

 

Bus manager capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the

 

 

 

host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power management capable. When set, this indicates that the node is power management capable.

27

 

pmc

 

R/W

 

Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see

 

 

 

 

 

 

 

 

 

Section 4.16) is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26±24

 

RSVD

 

 

R

 

Reserved. Bits 26±24 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle master clock accuracy, in parts per million. IEEE 1394 bus management field. Must be valid

23±16

cyc_clk_acc

 

R/W

 

when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16)

 

 

 

 

 

 

 

 

 

is set.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum request. IEEE 1394 bus management field. Hardware initializes this field to indicate the

 

 

 

 

 

 

 

 

 

maximum number of bytes in a block request packet that is supported by the implementation. This

 

 

 

 

 

 

 

 

 

value, max_rec_bytes must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may

15±12

max_rec

 

R/W

 

change this field; however, this field must be valid at any time bit 17 (linkEnable) of the host controller

 

 

 

 

 

 

 

 

 

control register (OHCI offset 50h/54h, see Section 4.16) is set. A received block write request packet

 

 

 

 

 

 

 

 

 

with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by

 

 

 

 

 

 

 

 

 

a soft reset, and defaults to a value indicating 2048 bytes on a hard reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11±8

 

RSVD

 

 

R

 

Reserved. Bits 11±8 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7±6

 

 

g

 

R/W

 

Generation counter. This field is incremented if any portion of the configuration ROM has been

 

 

 

 

incremented since the prior bus reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5±3

 

RSVD

 

 

R

 

Reserved. Bits 5±3 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2±0

Lnk_spd

 

 

R

 

Link speed. This field returns 010, indicating that the link speeds of 100, 200, and 400 Mbits/s are

 

 

 

supported.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4±9

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Page 46 Page 48
Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage PackageCCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC VccpTerminal Name ±1. Signals Sorted by Terminal NumberTerminal Description Name ±2. Signal Names Sorted Alphanumerically to Terminal Number±3. Power Supply Terminals As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers±2. PCI Configuration Register Map Vendor ID RegisterDevice ID Register Command RegisterCommand ±3. Command Register Description±4. Status Register Description Status RegisterStatus Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID RegisterOhci Base Address Register Header Type and Bist RegisterSubsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base addressRegister Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin RegisterOhci Control Register Mingnt and Maxlat RegisterCapabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer Nextitem±14. Power Management Capabilities Register Description Power Management Capabilities RegisterRegister Power management capabilities Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and status±17. Miscellaneous Configuration Register Miscellaneous Configuration RegisterMiscellaneous configuration ±18. Link Enhancement Control Register Description Link Enhancement Control RegisterLink enhancement control Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register Description±20. Gpio Control Register Description Gpio Control RegisterGpio control ±18 Guid ROM Guidrom ±1. Ohci Register MapDMA Context Register Name Abbreviation Offset Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClearAsynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatch±2. Ohci Version Register Description Ohci Version RegisterOhci version RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retriesCSR control CSR Compare RegisterCSR Control Register CSR compareBus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register Description±7. Bus Options Register Description Bus Options RegisterBus options Guid low Guid High RegisterGuid Low Register Guid highPosted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register DescriptionVendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register Description±10. Host Controller Control Register Description Host Controller Control RegisterHost controller control Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointerIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low Register±14. Interrupt Event Register Description Interrupt Event RegisterInterrupt event Arrq Rscu Arrs RscuRscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register DescriptionIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt eventFairness control Fairness Control RegisterFairness control ±18. Fairness Control Register Description±19. Link Control Register Description Link Control RegisterLink control CPS Node Identification RegisterNode identification ±20. Node Identification Register Description±21. PHY Control Register Description PHY Layer Control RegisterPHY layer control 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register Description±23. Asynchronous Request Filter High Register Description Asynchronous Request Filter High RegisterAsynchronous request filter high ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register DescriptionAre accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description±32 Physical request filter low Physical Request Filter Low RegisterPhysical request filter low ±26. Physical Request Filter Low Register Description±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper boundRscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register Description31±4 DescriptorAddress Asynchronous Context Command Pointer RegisterAsynchronous context command pointer RSC RSU Isochronous Transmit Context Control RegisterIsochronous transmit context control Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control RegisterMatch register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match±42 Gpio Interface Page 13h PCI register 40h PCI Ohci register ±1. Registers and Bits Loadable through Serial ROMROM Offset OHCI/PCI Offset Register Bits Loaded From ROM Rsvd PME ±2. Serial ROM MapByte Byte Description Address Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsUnit Recommended Operating ConditionsOperation MIN NOM Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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