Configuration ROM Mapping Register | Texas Instruments TSB12LV26

Texas Instruments TSB12LV26 Configuration ROM Mapping Register, Posted Write Address Low Register

Page 49

4.12 Configuration ROM Mapping Register

The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4±8 for a complete description of the register contents.

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

Name							Configuration ROM mapping

Type	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Default	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit	15	14	13		12		11		10	9	8	7	6		5	4	3	2	1	0
Name										Configuration ROM mapping

Type	R/W	R/W	R/W			R/W		R/W	R/W	R	R	R		R	R	R	R	R	R	R

Default	0	0	0			0		0	0	0	0	0		0	0	0	0	0	0	0
	Register:		Configuration ROM mapping
	Type:		Read/Write, Read-only
	Offset:		34h
	Default:		0000 0000h
			Table 4±8. Configuration ROM Mapping Register Description

BIT	FIELD NAME			TYPE									DESCRIPTION

							If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is
31±10	configROMaddr			R/W			received, then the low-order 10 bits of the offset are added to this register to determine the host memory
							address of the read request.

9±0	RSVD				R		Reserved. Bits 9±0 return 0s when read.

4.13 Posted Write Address Low Register

The posted write address low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. This register contains the lower 32 bits of the 1394 destination offset of the write request that failed.

Bit

Name

Posted write address low

Type

Default

Bit

Name

Posted write address low

Type

Default

Posted write address low

Type:

Read/Update

Offset:

38h

Default:

XXXX XXXXh

4±11

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Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOrdering Information Related DocumentsOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp Pciclkrun Pciinta 3.3 VCC PZ Package TOP ViewVccp CCPTerminal Name ±1. Signals Sorted by Terminal Number±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name PCIRST, terminal ±4. PCI System TerminalsPciclk As open-drain±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcic BE0 ±6. PCI Interface Control TerminalsIrdy Pcitrdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram ±2. PCI Configuration Register Map PCI Configuration RegistersVendor ID Register Register Name OffsetCommand Command Register±3. Command Register Description Device ID RegisterStatus Status Register±4. Status Register Description Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision IDOhci Base Address Register Header Type and Bist RegisterSubsystem Identification Register TI Extension Base Address RegisterTI extension base address Subsystem identificationRegister Power management capabilities pointer Power Management Capabilities Pointer RegisterInterrupt Line and Pin Register Register Interrupt line and pinOhci Control Register Mingnt and Maxlat RegisterRegister Capability ID and next item pointer Capability ID and Next Item Pointer RegisterNextitem CapabilityidRegister Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power Management Extension Register Power Management Control and Status RegisterPower management control and status Power management extensionMiscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description Subsystem access Subsystem Access Register±19. Subsystem Access Register Description SubdevidGpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous receive context command Isochronous transmit context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSetOhci version Ohci Version Register±2. Ohci Version Register Description ±3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSUCSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register Description CSR Control Register CSR Compare Register CSR compare CSR controlConfiguration ROM header Configuration ROM Header Register±6. Configuration ROM Header Register Description Bus Identification RegisterBus options Bus Options Register±7. Bus Options Register Description Guid Low Register Guid High RegisterGuid high Guid lowConfiguration ROM mapping Configuration ROM Mapping Register±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted write address high Posted Write Address High Register±9. Posted Write Address High Register Description Vendor IDHost controller control Host Controller Control Register±10. Host Controller Control Register Description Self-ID Count Register Self-ID Buffer Pointer RegisterSelf ID-buffer pointer Self-ID countIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrq Rscu Arrs RscuInterrupt mask Interrupt Mask Register±15. Interrupt Mask Register Description Rscu RSCIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Mask Register Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness control Fairness Control Register±18. Fairness Control Register Description Fairness controlLink control Link Control Register±19. Link Control Register Description Node identification Node Identification Register±20. Node Identification Register Description CPSPHY layer control PHY Layer Control Register±21. PHY Control Register Description Isochronous cycle timer Isochronous Cycle Timer Register±22. Isochronous Cycle Timer Register Description 24±12Asynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 Asynchronous request filter low Asynchronous Request Filter Low Register±24. Asynchronous Request Filter Low Register Description ±30Physical request filter high Physical Request Filter High Register±25. Physical Request Filter High Register Description Are accepted±32 Physical request filter low Physical Request Filter Low Register±26. Physical Request Filter Low Register Description Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34Asynchronous context control Asynchronous Context Control Register±27. Asynchronous Context Control Register Description Rscu RSUAsynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context controlReserved. Bits 27±16 return 0s when read CycleMatchEnableMultiChanMode Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous Receive Context Match Register When the command descriptor w field is set to 11bIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsOperation MIN NOM Recommended Operating ConditionsUnit Switching Characteristics for PHY-Link Interface§ Switching Characteristics for PCI Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

Texas Instruments TSB12LV26 Configuration ROM Mapping Register, Posted Write Address Low Register

4.12 Configuration ROM Mapping Register

Configuration ROM mapping

Table 4±8. Configuration ROM Mapping Register Description

BIT

31±10

configROMaddr

4.13 Posted Write Address Low Register

Posted write address low