Texas Instruments TSB12LV26 Miscellaneous Configuration Register, Miscellaneous configuration

Page 34

3.20 Miscellaneous Configuration Register

The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3±17 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

Miscellaneous configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

14

13

12

11

10

9

 

8

 

7

 

6

5

 

4

 

3

2

1

 

0

Name

 

 

 

 

 

 

 

 

 

Miscellaneous configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R/W

R

R/W

R

 

 

R

R/W

R

 

R

 

R

 

R

R

 

R/W

 

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

1

0

0

1

 

0

 

0

 

0

 

0

0

 

0

 

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register:

Miscellaneous configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type:

 

Read/Write, Read-only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset:

F0h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default:

0000 2400h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3±17. Miscellaneous Configuration Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

FIELD NAME

TYPE

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31±16

 

RSVD

 

R

 

 

Reserved. Bits 31±16 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

support from D3cold. This bit is used to program bit 15 (PME_D3COLD) in the power

15

PME_D3COLD

R/W

 

 

PCI_PME

 

 

management capabilities register (offset 46h, see Section 3.17).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

RSVD

 

R

 

 

Reserved. Bit 14 returns 0 when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

support. This bit is used to program bit 13 (PME_SUPPORT_D2) in the power

 

 

 

 

 

 

 

PCI_PME

13

PME_SUPPORT_D2

R/W

 

 

management capabilities register (offset 46h, see Section 3.17). If wake from the D2 power state

 

 

implemented in the TSB12LV26 is not desired, then this bit may be cleared to indicate to power

 

 

 

 

 

 

 

 

 

 

 

 

 

 

management software that wake-up from D2 is not supported.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12±11

 

RSVD

 

R

 

 

Reserved. Bits 12±11 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D2 support. This bit is used to program bit 10 (D2_SUPPORT) in the power management

10

D2_SUPPORT

R/W

 

 

capabilities register (offset 46h, see Section 3.17). If the D2 power state implemented in the

 

 

TSB12LV26 is not desired, then this bit may be cleared to indicate to power management software

 

 

 

 

 

 

 

 

 

 

 

 

 

 

that D2 is not supported.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9±5

 

RSVD

 

R

 

 

Reserved. Bits 9±5 return 0s when read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit defaults to 0, which provides OHCI-Lynx compatible target abort signaling. When this bit is

 

 

 

 

 

 

 

set to 1, it enables the no-target-abort mode, in which the TSB12LV26 returns indeterminate data

 

 

 

 

 

 

 

instead of signaling target abort.

 

 

 

 

 

 

 

 

 

 

 

 

4

DIS_TGT_ABT

R/W

 

 

The link is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the

 

 

link that are not active because the SCLK is disabled, a target abort is issued by the link. On some

 

 

 

 

 

 

 

 

 

 

 

 

 

 

systems this can cause a problem resulting in a fatal system error. Enabling this bit allows the link

 

 

 

 

 

 

 

to respond to these types of requests by returning FFh.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

It is recommended that this bit be set to 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

GP2IIC

 

R/W

 

 

When this bit is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA,

 

 

 

 

respectively. The GPIO3 and GPIO2 terminals are also placed in a high impedance state.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

DISABLE_SCLKGATE

R/W

 

 

When this bit is set to 1, the internal SCLK runs identically with the chip input. This bit is a test

 

 

feature only and should be cleared to 0 (all applications).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

DISABLE_PCIGATE

R/W

 

 

When this bit is set, the internal PCI clock runs identically with the chip input. This bit is a test

 

 

feature only and should be cleared to 0 (all applications).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When this bit is set to 1, the PCI clock is always kept running through the

 

 

protocol.

0

KEEP_PCLK

R/W

 

 

PCI_CLKRUN

 

 

When this bit is cleared, the PCI clock may be stopped using PCI_CLKRUN.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3±14

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables ViiViii Features DescriptionOrdering Number Name Voltage Package Related DocumentsOrdering Information OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC CCP±1. Signals Sorted by Terminal Number Terminal Name±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name Pciclk ±4. PCI System TerminalsPCIRST, terminal As open-drainDuring the data phase, AD31±AD0 contain data ±5. PCI Address and Data TerminalsIrdy ±6. PCI Interface Control TerminalsPcic BE0 Pcitrdy±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning±1. TSB12LV26 Block Diagram Vendor ID Register PCI Configuration Registers±2. PCI Configuration Register Map Register Name Offset±3. Command Register Description Command RegisterCommand Device ID RegisterStatus Status Register±4. Status Register Description Class Code and Revision ID Register Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class code and revision IDHeader Type and Bist Register Ohci Base Address RegisterTI extension base address TI Extension Base Address RegisterSubsystem Identification Register Subsystem identificationInterrupt Line and Pin Register Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Register Interrupt line and pinMingnt and Maxlat Register Ohci Control RegisterNextitem Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer CapabilityidRegister Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power management control and status Power Management Control and Status RegisterPower Management Extension Register Power management extensionMiscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description ±19. Subsystem Access Register Description Subsystem Access RegisterSubsystem access SubdevidGpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom PhysicalRequestFilterHiClear IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet Physical request filter low PhysicalRequestFilterLoSetCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Isochronous transmit context commandIsochronous receive context command Asynchronous context control ContextControlSetOhci version Ohci Version Register±2. Ohci Version Register Description Guid ROM Guid ROM Register±3. Guid ROM Register Description RSUAsynchronous transmit retries Asynchronous Transmit Retries RegisterCSR Data Register ±4. Asynchronous Transmit Retries Register DescriptionCSR compare CSR Compare RegisterCSR Control Register CSR control±6. Configuration ROM Header Register Description Configuration ROM Header RegisterConfiguration ROM header Bus Identification RegisterBus options Bus Options Register±7. Bus Options Register Description Guid high Guid High RegisterGuid Low Register Guid low±8. Configuration ROM Mapping Register Description Configuration ROM Mapping RegisterConfiguration ROM mapping Posted Write Address Low Register±9. Posted Write Address High Register Description Posted Write Address High RegisterPosted write address high Vendor IDHost controller control Host Controller Control Register±10. Host Controller Control Register Description Self ID-buffer pointer Self-ID Buffer Pointer RegisterSelf-ID Count Register Self-ID countIsochronous Receive Channel Mask High Register Isochronous receive channel mask highIsochronous Receive Channel Mask Low Register Isochronous receive channel mask lowInterrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrs Rscu Arrq Rscu±15. Interrupt Mask Register Description Interrupt Mask RegisterInterrupt mask Rscu RSCIsochronous Transmit Interrupt Event Register Isochronous transmit interrupt event±21 Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask Isochronous transmit interrupt maskIsochronous receive interrupt event Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt mask±18. Fairness Control Register Description Fairness Control RegisterFairness control Fairness controlLink control Link Control Register±19. Link Control Register Description ±20. Node Identification Register Description Node Identification RegisterNode identification CPSPHY layer control PHY Layer Control Register±21. PHY Control Register Description ±22. Isochronous Cycle Timer Register Description Isochronous Cycle Timer RegisterIsochronous cycle timer 24±12Asynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 ±24. Asynchronous Request Filter Low Register Description Asynchronous Request Filter Low RegisterAsynchronous request filter low ±30±25. Physical Request Filter High Register Description Physical Request Filter High RegisterPhysical request filter high Are accepted±32 ±26. Physical Request Filter Low Register Description Physical Request Filter Low RegisterPhysical request filter low Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34±27. Asynchronous Context Control Register Description Asynchronous Context Control RegisterAsynchronous context control Rscu RSUAsynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous Receive Context Control Register Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous receive context controlMultiChanMode CycleMatchEnableReserved. Bits 27±16 return 0s when read Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous receive context match When the command descriptor w field is set to 11bIsochronous Receive Context Match Register ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges²Operation MIN NOM Recommended Operating ConditionsUnit Operation Test MIN MAX Unit Conditions Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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