Texas Instruments TSB12LV26 manual Power Management Capabilities Pointer Register

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3.12 Power Management Capabilities Pointer Register

The power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. The TSB12LV26 configuration header double-words at offsets 44h and 48h provide the power management registers. This register is read-only and returns 44h when read.

Bit

7

6

5

 

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

Power management capabilities pointer

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

 

R

R

 

R

R

R

 

 

 

 

 

 

 

 

 

 

 

Default

0

1

0

 

0

0

 

1

0

0

 

 

 

 

 

 

 

 

 

 

 

Register: Power management capabilities pointer

Type: Read-only

Offset: 34h

Default: 44h

3.13 Interrupt Line and Pin Register

The interrupt line and pin register is used to communicate interrupt line routing information. See Table 3±10 for a complete description of the register contents.

Bit

15

14

13

12

11

10

9

 

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

 

Interrupt line and pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

R

R

R

R

R

R

R

 

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

0

0

0

0

0

0

0

 

1

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register: Interrupt line and pin

Type: Read/Write, Read-only

Offset: 3Ch

Default: 0100h

Table 3±10. Interrupt Line and Pin Register Description

BIT

FIELD NAME

TYPE

 

 

DESCRIPTION

 

 

 

 

 

 

15±8

INTR_PIN

R

Interrupt pin. Returns 01h when read, indicating that the TSB12LV26 PCI function signals interrupts on

the PCI_INTA pin.

 

 

 

 

 

 

 

7±0

INTR_LINE

R/W

Interrupt line. This field is programmed by the system and indicates to software which interrupt line the

 

 

 

TSB12LV26 PCI_INTA is connected to.

 

 

 

 

 

 

 

 

 

3±9

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOrdering Information Related DocumentsOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerVccp Pciclkrun Pciinta 3.3 VCC PZ Package TOP ViewVccp CCPTerminal Name ±1. Signals Sorted by Terminal NumberTerminal Description Name ±2. Signal Names Sorted Alphanumerically to Terminal Number±3. Power Supply Terminals PCIRST, terminal ±4. PCI System TerminalsPciclk As open-drain±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcic BE0 ±6. PCI Interface Control TerminalsIrdy Pcitrdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram ±2. PCI Configuration Register Map PCI Configuration RegistersVendor ID Register Register Name OffsetCommand Command Register±3. Command Register Description Device ID Register±4. Status Register Description Status RegisterStatus Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision IDOhci Base Address Register Header Type and Bist RegisterSubsystem Identification Register TI Extension Base Address RegisterTI extension base address Subsystem identificationRegister Power management capabilities pointer Power Management Capabilities Pointer RegisterInterrupt Line and Pin Register Register Interrupt line and pinOhci Control Register Mingnt and Maxlat RegisterRegister Capability ID and next item pointer Capability ID and Next Item Pointer RegisterNextitem Capabilityid±14. Power Management Capabilities Register Description Power Management Capabilities RegisterRegister Power management capabilities Power Management Extension Register Power Management Control and Status RegisterPower management control and status Power management extension±17. Miscellaneous Configuration Register Miscellaneous Configuration RegisterMiscellaneous configuration ±18. Link Enhancement Control Register Description Link Enhancement Control RegisterLink enhancement control Subsystem access Subsystem Access Register±19. Subsystem Access Register Description Subdevid±20. Gpio Control Register Description Gpio Control RegisterGpio control ±18 Guid ROM Guidrom ±1. Ohci Register MapDMA Context Register Name Abbreviation Offset Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous receive context command Isochronous transmit context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSet±2. Ohci Version Register Description Ohci Version RegisterOhci version ±3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSUCSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Control Register CSR Compare RegisterCSR compare CSR controlConfiguration ROM header Configuration ROM Header Register±6. Configuration ROM Header Register Description Bus Identification Register±7. Bus Options Register Description Bus Options RegisterBus options Guid Low Register Guid High RegisterGuid high Guid lowConfiguration ROM mapping Configuration ROM Mapping Register±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted write address high Posted Write Address High Register±9. Posted Write Address High Register Description Vendor ID±10. Host Controller Control Register Description Host Controller Control RegisterHost controller control Self-ID Count Register Self-ID Buffer Pointer RegisterSelf ID-buffer pointer Self-ID countIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low Register±14. Interrupt Event Register Description Interrupt Event RegisterInterrupt event Arrq Rscu Arrs RscuInterrupt mask Interrupt Mask Register±15. Interrupt Mask Register Description Rscu RSCIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Mask Register Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness control Fairness Control Register±18. Fairness Control Register Description Fairness control±19. Link Control Register Description Link Control RegisterLink control Node identification Node Identification Register±20. Node Identification Register Description CPS±21. PHY Control Register Description PHY Layer Control RegisterPHY layer control Isochronous cycle timer Isochronous Cycle Timer Register±22. Isochronous Cycle Timer Register Description 24±12±23. Asynchronous Request Filter High Register Description Asynchronous Request Filter High RegisterAsynchronous request filter high ±29 Asynchronous request filter low Asynchronous Request Filter Low Register±24. Asynchronous Request Filter Low Register Description ±30Physical request filter high Physical Request Filter High Register±25. Physical Request Filter High Register Description Are accepted±32 Physical request filter low Physical Request Filter Low Register±26. Physical Request Filter Low Register Description Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34Asynchronous context control Asynchronous Context Control Register±27. Asynchronous Context Control Register Description Rscu RSU31±4 DescriptorAddress Asynchronous Context Command Pointer RegisterAsynchronous context command pointer RSC RSU Isochronous Transmit Context Control RegisterIsochronous transmit context control Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context controlReserved. Bits 27±16 return 0s when read CycleMatchEnableMultiChanMode Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous Receive Context Match Register When the command descriptor w field is set to 11bIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page 13h PCI register 40h PCI Ohci register ±1. Registers and Bits Loadable through Serial ROMROM Offset OHCI/PCI Offset Register Bits Loaded From ROM Rsvd PME ±2. Serial ROM MapByte Byte Description Address Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsUnit Recommended Operating ConditionsOperation MIN NOM Switching Characteristics for PHY-Link Interface§ Switching Characteristics for PCI Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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