Physical upper bound, ±34 | Texas Instruments TSB12LV26 specification

Texas Instruments TSB12LV26 Physical Upper Bound Register Optional Register, Physical upper bound

Page 72

4.36 Physical Upper Bound Register (Optional Register)

The physical upper bound register is an optional register and is not implemented. It returns all 0s when read.

Bit	31	30	29	28	27	26	25		24	23	22	21	20	19	18	17	16

Name								Physical upper bound

Type	R	R	R	R	R	R	R		R	R	R	R	R	R	R	R	R

Default	0	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0

Bit	15	14	13	12	11	10	9	8		7	6	5	4	3	2	1	0
Name								Physical upper bound

Type	R	R	R	R	R	R	R		R	R	R	R	R	R	R	R	R

Default	0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0
	Register:		Physical upper bound
	Type:		Read-only
	Offset:		120h
	Default:		0000 0000h

4±34

Image 72

Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations List of Tables ViiViii Features DescriptionRelated Documents Ordering InformationOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host ControllerPZ Package TOP View Vccp Pciclkrun Pciinta 3.3 VCCVccp CCP±1. Signals Sorted by Terminal Number Terminal Name±2. Signal Names Sorted Alphanumerically to Terminal Number ±3. Power Supply TerminalsTerminal Description Name ±4. PCI System Terminals PCIRST, terminalPciclk As open-drainDuring the data phase, AD31±AD0 contain data ±5. PCI Address and Data Terminals±6. PCI Interface Control Terminals Pcic BE0Irdy Pcitrdy±7. Ieee 1394 PHY/Link Terminals ±8. Miscellaneous TerminalsPage ±1. Bit Field Access Tag Descriptions Access TAG Name Meaning±1. TSB12LV26 Block Diagram PCI Configuration Registers ±2. PCI Configuration Register MapVendor ID Register Register Name OffsetCommand Register Command±3. Command Register Description Device ID RegisterStatus Register Status±4. Status Register Description Latency Timer and Class Cache Line Size Register Latency timer and class cache line sizeClass Code and Revision ID Register Class code and revision IDHeader Type and Bist Register Ohci Base Address RegisterTI Extension Base Address Register Subsystem Identification RegisterTI extension base address Subsystem identificationPower Management Capabilities Pointer Register Register Power management capabilities pointerInterrupt Line and Pin Register Register Interrupt line and pinMingnt and Maxlat Register Ohci Control RegisterCapability ID and Next Item Pointer Register Register Capability ID and next item pointerNextitem CapabilityidPower Management Capabilities Register Register Power management capabilities±14. Power Management Capabilities Register Description Power Management Control and Status Register Power Management Extension RegisterPower management control and status Power management extensionMiscellaneous Configuration Register Miscellaneous configuration±17. Miscellaneous Configuration Register Link Enhancement Control Register Link enhancement control±18. Link Enhancement Control Register Description Subsystem Access Register Subsystem access±19. Subsystem Access Register Description SubdevidGpio Control Register Gpio control±20. Gpio Control Register Description ±18 ±1. Ohci Register Map DMA Context Register Name Abbreviation OffsetGuid ROM Guidrom IsoRecvIntEventClear Isochronous receive interrupt mask IsoRecvIntMaskSetPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous transmit context command Isochronous receive context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSetOhci Version Register Ohci version±2. Ohci Version Register Description Guid ROM Register ±3. Guid ROM Register DescriptionGuid ROM RSUAsynchronous Transmit Retries Register CSR Data RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Compare Register CSR Control RegisterCSR compare CSR controlConfiguration ROM Header Register Configuration ROM header±6. Configuration ROM Header Register Description Bus Identification RegisterBus Options Register Bus options±7. Bus Options Register Description Guid High Register Guid Low RegisterGuid high Guid lowConfiguration ROM Mapping Register Configuration ROM mapping±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted Write Address High Register Posted write address high±9. Posted Write Address High Register Description Vendor IDHost Controller Control Register Host controller control±10. Host Controller Control Register Description Self-ID Buffer Pointer Register Self-ID Count RegisterSelf ID-buffer pointer Self-ID countIsochronous Receive Channel Mask High Register Isochronous receive channel mask highIsochronous Receive Channel Mask Low Register Isochronous receive channel mask lowInterrupt Event Register Interrupt event±14. Interrupt Event Register Description Arrs Rscu Arrq RscuInterrupt Mask Register Interrupt mask±15. Interrupt Mask Register Description Rscu RSCIsochronous Transmit Interrupt Event Register Isochronous transmit interrupt eventIsochronous Transmit Interrupt Mask Register Isochronous transmit interrupt mask±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Event Register Isochronous Receive Interrupt Mask RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness Control Register Fairness control±18. Fairness Control Register Description Fairness controlLink Control Register Link control±19. Link Control Register Description Node Identification Register Node identification±20. Node Identification Register Description CPSPHY Layer Control Register PHY layer control±21. PHY Control Register Description Isochronous Cycle Timer Register Isochronous cycle timer±22. Isochronous Cycle Timer Register Description 24±12Asynchronous Request Filter High Register Asynchronous request filter high±23. Asynchronous Request Filter High Register Description ±29 Asynchronous Request Filter Low Register Asynchronous request filter low ±24. Asynchronous Request Filter Low Register Description ±30Physical Request Filter High Register Physical request filter high±25. Physical Request Filter High Register Description Are accepted±32 Physical Request Filter Low Register Physical request filter low±26. Physical Request Filter Low Register Description Physical request filter lowPhysical Upper Bound Register Optional Register Physical upper boundPhysical upper bound ±34Asynchronous Context Control Register Asynchronous context control±27. Asynchronous Context Control Register Description Rscu RSUAsynchronous Context Command Pointer Register Asynchronous context command pointer31±4 DescriptorAddress Isochronous Transmit Context Control Register Isochronous transmit context controlRSC RSU Isochronous Transmit Context Command Pointer Register Isochronous transmit context command pointerIsochronous Receive Context Control Register Isochronous receive context controlCycleMatchEnable Reserved. Bits 27±16 return 0s when readMultiChanMode Match register see .43 is ignoredIsochronous Receive Context Command Pointer Register Isochronous receive context command pointerIsochronous receive context command pointer ±40When the command descriptor w field is set to 11b Isochronous Receive Context Match RegisterIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page ±1. Registers and Bits Loadable through Serial ROM ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM13h PCI register 40h PCI Ohci register ±2. Serial ROM Map Byte Byte Description AddressRsvd PME Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges²Recommended Operating Conditions Operation MIN NOMUnit Switching Characteristics for PCI Interface§ Switching Characteristics for PHY-Link Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage Mechanical Information PZ S-PQFP-G100Page Important Notice

Texas Instruments TSB12LV26 Physical Upper Bound Register Optional Register, Physical upper bound

4.36 Physical Upper Bound Register (Optional Register)

Physical upper bound

Physical upper bound

Physical upper bound

4±34