Texas Instruments
TSB12LV26
manual
Electrical Characteristics
±1. TSB12LV26 Block Diagram
Isochronous cycle timer
PCI Configuration Registers
Access TAG Name Meaning
Command Register
±3. Power Supply Terminals
CycleMatchEnable
Features
Page 82
5±2
Page 81
Page 83
Image 82
Page 81
Page 83
Contents
Data Manual
SLLS366A
TSB12LV26
Important Notice
Contents
Page
Mechanical Information
List of Illustrations
List of Tables
Vii
Viii
Features
Description
Ordering Number Name Voltage Package
Related Documents
Ordering Information
OHCI-Lynx PCI-Based Ieee 1394 Host Controller
Vccp
PZ Package TOP View
Vccp Pciclkrun Pciinta 3.3 VCC
CCP
±1. Signals Sorted by Terminal Number
Terminal Name
±3. Power Supply Terminals
±2. Signal Names Sorted Alphanumerically to Terminal Number
Terminal Description Name
Pciclk
±4. PCI System Terminals
PCIRST, terminal
As open-drain
During the data phase, AD31±AD0 contain data
±5. PCI Address and Data Terminals
Irdy
±6. PCI Interface Control Terminals
Pcic BE0
Pcitrdy
±7. Ieee 1394 PHY/Link Terminals
±8. Miscellaneous Terminals
Page
±1. Bit Field Access Tag Descriptions
Access TAG Name Meaning
±1. TSB12LV26 Block Diagram
Vendor ID Register
PCI Configuration Registers
±2. PCI Configuration Register Map
Register Name Offset
±3. Command Register Description
Command Register
Command
Device ID Register
Status
Status Register
±4. Status Register Description
Class Code and Revision ID Register
Latency Timer and Class Cache Line Size Register
Latency timer and class cache line size
Class code and revision ID
Header Type and Bist Register
Ohci Base Address Register
TI extension base address
TI Extension Base Address Register
Subsystem Identification Register
Subsystem identification
Interrupt Line and Pin Register
Power Management Capabilities Pointer Register
Register Power management capabilities pointer
Register Interrupt line and pin
Mingnt and Maxlat Register
Ohci Control Register
Nextitem
Capability ID and Next Item Pointer Register
Register Capability ID and next item pointer
Capabilityid
Register Power management capabilities
Power Management Capabilities Register
±14. Power Management Capabilities Register Description
Power management control and status
Power Management Control and Status Register
Power Management Extension Register
Power management extension
Miscellaneous configuration
Miscellaneous Configuration Register
±17. Miscellaneous Configuration Register
Link enhancement control
Link Enhancement Control Register
±18. Link Enhancement Control Register Description
±19. Subsystem Access Register Description
Subsystem Access Register
Subsystem access
Subdevid
Gpio control
Gpio Control Register
±20. Gpio Control Register Description
±18
DMA Context Register Name Abbreviation Offset
±1. Ohci Register Map
Guid ROM Guidrom
PhysicalRequestFilterHiClear
IsoRecvIntEventClear
Isochronous receive interrupt mask IsoRecvIntMaskSet
Physical request filter low PhysicalRequestFilterLoSet
CommandPtr 40Ch + 32*n Pointer Context match ContextMatch
Isochronous transmit context command
Isochronous receive context command
Asynchronous context control ContextControlSet
Ohci version
Ohci Version Register
±2. Ohci Version Register Description
Guid ROM
Guid ROM Register
±3. Guid ROM Register Description
RSU
Asynchronous transmit retries
Asynchronous Transmit Retries Register
CSR Data Register
±4. Asynchronous Transmit Retries Register Description
CSR compare
CSR Compare Register
CSR Control Register
CSR control
±6. Configuration ROM Header Register Description
Configuration ROM Header Register
Configuration ROM header
Bus Identification Register
Bus options
Bus Options Register
±7. Bus Options Register Description
Guid high
Guid High Register
Guid Low Register
Guid low
±8. Configuration ROM Mapping Register Description
Configuration ROM Mapping Register
Configuration ROM mapping
Posted Write Address Low Register
±9. Posted Write Address High Register Description
Posted Write Address High Register
Posted write address high
Vendor ID
Host controller control
Host Controller Control Register
±10. Host Controller Control Register Description
Self ID-buffer pointer
Self-ID Buffer Pointer Register
Self-ID Count Register
Self-ID count
Isochronous Receive Channel Mask High Register
Isochronous receive channel mask high
Isochronous Receive Channel Mask Low Register
Isochronous receive channel mask low
Interrupt event
Interrupt Event Register
±14. Interrupt Event Register Description
Arrs Rscu
Arrq Rscu
±15. Interrupt Mask Register Description
Interrupt Mask Register
Interrupt mask
Rscu RSC
Isochronous Transmit Interrupt Event Register
Isochronous transmit interrupt event
±21
Isochronous Transmit Interrupt Mask Register
Isochronous transmit interrupt mask
Isochronous transmit interrupt mask
Isochronous receive interrupt event
Isochronous Receive Interrupt Event Register
Isochronous Receive Interrupt Mask Register
Isochronous receive interrupt mask
±18. Fairness Control Register Description
Fairness Control Register
Fairness control
Fairness control
Link control
Link Control Register
±19. Link Control Register Description
±20. Node Identification Register Description
Node Identification Register
Node identification
CPS
PHY layer control
PHY Layer Control Register
±21. PHY Control Register Description
±22. Isochronous Cycle Timer Register Description
Isochronous Cycle Timer Register
Isochronous cycle timer
24±12
Asynchronous request filter high
Asynchronous Request Filter High Register
±23. Asynchronous Request Filter High Register Description
±29
±24. Asynchronous Request Filter Low Register Description
Asynchronous Request Filter Low Register
Asynchronous request filter low
±30
±25. Physical Request Filter High Register Description
Physical Request Filter High Register
Physical request filter high
Are accepted
±32
±26. Physical Request Filter Low Register Description
Physical Request Filter Low Register
Physical request filter low
Physical request filter low
Physical upper bound
Physical Upper Bound Register Optional Register
Physical upper bound
±34
±27. Asynchronous Context Control Register Description
Asynchronous Context Control Register
Asynchronous context control
Rscu RSU
Asynchronous context command pointer
Asynchronous Context Command Pointer Register
31±4 DescriptorAddress
Isochronous transmit context control
Isochronous Transmit Context Control Register
RSC RSU
Isochronous Receive Context Control Register
Isochronous Transmit Context Command Pointer Register
Isochronous transmit context command pointer
Isochronous receive context control
MultiChanMode
CycleMatchEnable
Reserved. Bits 27±16 return 0s when read
Match register see .43 is ignored
Isochronous receive context command pointer
Isochronous Receive Context Command Pointer Register
Isochronous receive context command pointer
±40
Isochronous receive context match
When the command descriptor w field is set to 11b
Isochronous Receive Context Match Register
±31. Isochronous Receive Context Match Register Description
±42
Gpio Interface
Page
ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM
±1. Registers and Bits Loadable through Serial ROM
13h PCI register 40h PCI Ohci register
Byte Byte Description Address
±2. Serial ROM Map
Rsvd PME
Electrical Characteristics
Absolute Maximum Ratings Over Operating Temperature Ranges²
Operation MIN NOM
Recommended Operating Conditions
Unit
Operation Test MIN MAX Unit Conditions
Switching Characteristics for PCI Interface§
Switching Characteristics for PHY-Link Interface§
Parameter Measured MIN TYP MAX Unit
Page
Mechanical Information
PZ S-PQFP-G100
Page
Important Notice
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