±5. PCI Address and Data Terminals | Texas Instruments TSB12LV26

Texas Instruments TSB12LV26 manual ±5. PCI Address and Data Terminals

Page 17

			Table 2±5. PCI Address and Data Terminals
TERMINAL		I/O	DESCRIPTION

NAME	NO.
NAME	NO.

PCI_AD31	18
PCI_AD30	19
PCI_AD29	21
PCI_AD28	22
PCI_AD27	23
PCI_AD26	25
PCI_AD25	26
PCI_AD24	27
PCI_AD23	31
PCI_AD22	32
PCI_AD21	33
PCI_AD20	34
PCI_AD19	36
PCI_AD18	37
PCI_AD17	38		PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface.
PCI_AD16	40
PCI_AD16	40	I/O	During the address phase of a PCI cycle, AD31±AD0 contain a 32-bit address or other destination information.
PCI_AD15	54	I/O
PCI_AD15	54		During the data phase, AD31±AD0 contain data.
PCI_AD14	56		During the data phase, AD31±AD0 contain data.
PCI_AD14	56
PCI_AD13	57
PCI_AD12	58
PCI_AD11	59
PCI_AD10	61
PCI_AD9	62
PCI_AD8	64
PCI_AD7	66
PCI_AD6	67
PCI_AD5	68
PCI_AD4	69
PCI_AD3	71
PCI_AD2	72
PCI_AD1	73
PCI_AD0	74

2±5

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Contents

Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOrdering Information Related DocumentsOrdering Number Name Voltage Package OHCI-Lynx PCI-Based Ieee 1394 Host Controller Vccp Pciclkrun Pciinta 3.3 VCC PZ Package TOP View Vccp CCPTerminal Name ±1. Signals Sorted by Terminal NumberTerminal Description Name ±2. Signal Names Sorted Alphanumerically to Terminal Number±3. Power Supply Terminals PCIRST, terminal ±4. PCI System TerminalsPciclk As open-drain±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcic BE0 ±6. PCI Interface Control TerminalsIrdy Pcitrdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram ±2. PCI Configuration Register Map PCI Configuration RegistersVendor ID Register Register Name OffsetCommand Command Register±3. Command Register Description Device ID Register±4. Status Register Description Status RegisterStatus Latency timer and class cache line size Latency Timer and Class Cache Line Size RegisterClass Code and Revision ID Register Class code and revision IDOhci Base Address Register Header Type and Bist RegisterSubsystem Identification Register TI Extension Base Address RegisterTI extension base address Subsystem identificationRegister Power management capabilities pointer Power Management Capabilities Pointer RegisterInterrupt Line and Pin Register Register Interrupt line and pinOhci Control Register Mingnt and Maxlat RegisterRegister Capability ID and next item pointer Capability ID and Next Item Pointer RegisterNextitem Capabilityid±14. Power Management Capabilities Register Description Power Management Capabilities RegisterRegister Power management capabilities Power Management Extension Register Power Management Control and Status RegisterPower management control and status Power management extension±17. Miscellaneous Configuration Register Miscellaneous Configuration RegisterMiscellaneous configuration ±18. Link Enhancement Control Register Description Link Enhancement Control RegisterLink enhancement control Subsystem access Subsystem Access Register±19. Subsystem Access Register Description Subdevid±20. Gpio Control Register Description Gpio Control RegisterGpio control ±18 Guid ROM Guidrom ±1. Ohci Register MapDMA Context Register Name Abbreviation Offset Isochronous receive interrupt mask IsoRecvIntMaskSet IsoRecvIntEventClearPhysicalRequestFilterHiClear Physical request filter low PhysicalRequestFilterLoSetIsochronous receive context command Isochronous transmit context commandCommandPtr 40Ch + 32*n Pointer Context match ContextMatch Asynchronous context control ContextControlSet±2. Ohci Version Register Description Ohci Version RegisterOhci version ±3. Guid ROM Register Description Guid ROM RegisterGuid ROM RSUCSR Data Register Asynchronous Transmit Retries RegisterAsynchronous transmit retries ±4. Asynchronous Transmit Retries Register DescriptionCSR Control Register CSR Compare RegisterCSR compare CSR controlConfiguration ROM header Configuration ROM Header Register±6. Configuration ROM Header Register Description Bus Identification Register±7. Bus Options Register Description Bus Options RegisterBus options Guid Low Register Guid High RegisterGuid high Guid lowConfiguration ROM mapping Configuration ROM Mapping Register±8. Configuration ROM Mapping Register Description Posted Write Address Low RegisterPosted write address high Posted Write Address High Register±9. Posted Write Address High Register Description Vendor ID±10. Host Controller Control Register Description Host Controller Control RegisterHost controller control Self-ID Count Register Self-ID Buffer Pointer RegisterSelf ID-buffer pointer Self-ID countIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low Register±14. Interrupt Event Register Description Interrupt Event RegisterInterrupt event Arrq Rscu Arrs RscuInterrupt mask Interrupt Mask Register±15. Interrupt Mask Register Description Rscu RSCIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask Register±21 Isochronous transmit interrupt maskIsochronous Receive Interrupt Mask Register Isochronous Receive Interrupt Event RegisterIsochronous receive interrupt event Isochronous receive interrupt maskFairness control Fairness Control Register±18. Fairness Control Register Description Fairness control±19. Link Control Register Description Link Control RegisterLink control Node identification Node Identification Register±20. Node Identification Register Description CPS±21. PHY Control Register Description PHY Layer Control RegisterPHY layer control Isochronous cycle timer Isochronous Cycle Timer Register±22. Isochronous Cycle Timer Register Description 24±12±23. Asynchronous Request Filter High Register Description Asynchronous Request Filter High RegisterAsynchronous request filter high ±29 Asynchronous request filter low Asynchronous Request Filter Low Register±24. Asynchronous Request Filter Low Register Description ±30Physical request filter high Physical Request Filter High Register±25. Physical Request Filter High Register Description Are accepted±32 Physical request filter low Physical Request Filter Low Register±26. Physical Request Filter Low Register Description Physical request filter lowPhysical upper bound Physical Upper Bound Register Optional RegisterPhysical upper bound ±34Asynchronous context control Asynchronous Context Control Register±27. Asynchronous Context Control Register Description Rscu RSU31±4 DescriptorAddress Asynchronous Context Command Pointer RegisterAsynchronous context command pointer RSC RSU Isochronous Transmit Context Control RegisterIsochronous transmit context control Isochronous transmit context command pointer Isochronous Transmit Context Command Pointer RegisterIsochronous Receive Context Control Register Isochronous receive context controlReserved. Bits 27±16 return 0s when read CycleMatchEnableMultiChanMode Match register see .43 is ignoredIsochronous receive context command pointer Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer ±40Isochronous Receive Context Match Register When the command descriptor w field is set to 11bIsochronous receive context match ±31. Isochronous Receive Context Match Register Description±42 Gpio Interface Page 13h PCI register 40h PCI Ohci register ±1. Registers and Bits Loadable through Serial ROMROM Offset OHCI/PCI Offset Register Bits Loaded From ROM Rsvd PME ±2. Serial ROM MapByte Byte Description Address Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsUnit Recommended Operating ConditionsOperation MIN NOM Switching Characteristics for PHY-Link Interface§ Switching Characteristics for PCI Interface§Operation Test MIN MAX Unit Conditions Parameter Measured MIN TYP MAX UnitPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

Texas Instruments TSB12LV26 manual ±5. PCI Address and Data Terminals

Table 2±5. PCI Address and Data Terminals

TERMINAL

During the data phase, AD31±AD0 contain data.