Texas Instruments TSB12LV26 manual ±7. Ieee 1394 PHY/Link Terminals, ±8. Miscellaneous Terminals

Page 19

 

 

 

 

Table 2±7. IEEE 1394 PHY/Link Terminals

TERMINAL

 

I/O

DESCRIPTION

 

 

 

NAME

 

NO.

 

 

 

 

 

 

 

 

PHY_CTL1

 

92

 

PHY-link interface control. These bidirectional signals control passage of information between the two devices.

 

I/O

The TSB12LV26 can only drive these terminals after the PHY has granted permission following a link request

PHY_CTL0

 

93

 

 

(PHY_LREQ).

 

 

 

 

 

 

 

 

 

PHY_DATA7

 

81

 

 

PHY_DATA6

 

82

 

 

PHY_DATA5

 

84

 

PHY-link interface data. These bidirectional signals pass data between the TSB12LV26 and the PHY device.

PHY_DATA4

 

85

I/O

These terminals are driven by the TSB12LV26 on transmissions and are driven by the PHY on reception. Only

PHY_DATA3

 

86

PHY_DATA1±PHY_DATA0 are valid for 100-Mbit speeds, PHY_DATA3±PHY_DATA0 are valid for 200-Mbit

 

 

PHY_DATA2

 

88

 

speeds, and PHY_DATA7±PHY_DATA0 are valid for 400-Mbit speeds.

PHY_DATA1

 

89

 

 

PHY_DATA0

 

90

 

 

 

 

 

 

 

 

 

 

 

LinkOn wake indication. The PHY_LINKON signal is pulsed by the PHY to activate the link, and 3.3-V signaling

PHY_LINKON

 

98

I/O

is required.

 

When connected to the TSB41LV0X C/LKON terminal, a 1-kΩseries resistor is required between the link and

 

 

 

 

 

 

 

 

PHY.

 

 

 

 

 

PHY_LPS

 

99

I/O

Link power status. The PHY_LPS signal is asserted when the link is powered on, and 3.3-V signaling is

 

required.

 

 

 

 

 

 

 

 

 

PHY_LREQ

 

97

O

Link request. This signal is driven by the TSB12LV26 to initiate a request for the PHY to perform some service.

 

 

 

 

 

PHY_SCLK

 

95

I

System clock. This input from the PHY provides a 49.152-MHz clock signal for data synchronization.

 

 

 

 

 

 

Table 2±8. Miscellaneous Terminals

 

TERMINAL

 

I/O

DESCRIPTION

 

 

 

 

 

 

NAME

 

NO.

 

 

 

 

 

 

 

 

 

 

 

 

CYCLEOUT

 

77

I/O

This terminal provides an 8-kHz cycle timer synchronization signal.

 

 

 

 

 

 

 

 

 

 

 

 

 

The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other

 

CYCLEIN

 

78

I/O

system devices.

 

 

 

 

 

 

If this terminal is not implemented, then it should be pulled high to the link VCC through a 4.7-kΩresistor.

 

GPIO2

 

2

I/O

General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, then it is recommended

 

 

that it be pulled low to ground with a 220-Ωresistor.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GPIO3

 

3

I/O

General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, then it is recommended

 

 

that it be pulled low to ground with a 220-Ωresistor.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

79

I

Regulator enable. This terminal is pulled low to ground through a 220-Ωresistor.

 

REG_EN

 

 

 

 

 

 

 

 

 

 

REG18

 

42

I

The REG18 terminals are connected to a 0.01 ∝F capacitor which, in turn, is connected to ground. The

 

 

100

capacitor provides a local bypass for the internal core voltage.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial clock. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire

 

 

 

 

 

 

serial ROM is implemented, then this terminal provides the SCL serial clock signaling.

 

SCL

 

4

I/O

This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),

 

 

 

 

 

 

this terminal should be pulled high to the ROM VCC with a 2.7-kΩresistor. Otherwise, it should be pulled low

 

 

 

 

 

 

to ground with a 220-Ωresistor.

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial data. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire

 

 

 

 

 

 

serial ROM is detected, then this terminal provides the SDA serial data signaling. This terminal must be wired

 

SDA

 

5

I/O

low to indicate no serial ROM is present.

 

 

This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),

 

 

 

 

 

 

 

 

 

 

 

 

this terminal should be pulled high to the ROM VCC with a 2.7-kΩresistor. Otherwise, it should be pulled low

 

 

 

 

 

 

to ground with a 220-Ωresistor.

2±7

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Contents Data Manual SLLS366A TSB12LV26 Important Notice Contents Page Mechanical Information List of Illustrations Vii List of TablesViii Description FeaturesOHCI-Lynx PCI-Based Ieee 1394 Host Controller Related DocumentsOrdering Information Ordering Number Name Voltage PackageCCP PZ Package TOP ViewVccp Pciclkrun Pciinta 3.3 VCC VccpTerminal Name ±1. Signals Sorted by Terminal Number±3. Power Supply Terminals ±2. Signal Names Sorted Alphanumerically to Terminal NumberTerminal Description Name As open-drain ±4. PCI System TerminalsPCIRST, terminal Pciclk±5. PCI Address and Data Terminals During the data phase, AD31±AD0 contain dataPcitrdy ±6. PCI Interface Control TerminalsPcic BE0 Irdy±8. Miscellaneous Terminals ±7. Ieee 1394 PHY/Link TerminalsPage Access TAG Name Meaning ±1. Bit Field Access Tag Descriptions±1. TSB12LV26 Block Diagram Register Name Offset PCI Configuration Registers±2. PCI Configuration Register Map Vendor ID RegisterDevice ID Register Command RegisterCommand ±3. Command Register DescriptionStatus Status Register±4. Status Register Description Class code and revision ID Latency Timer and Class Cache Line Size RegisterLatency timer and class cache line size Class Code and Revision ID RegisterOhci Base Address Register Header Type and Bist RegisterSubsystem identification TI Extension Base Address RegisterSubsystem Identification Register TI extension base addressRegister Interrupt line and pin Power Management Capabilities Pointer RegisterRegister Power management capabilities pointer Interrupt Line and Pin RegisterOhci Control Register Mingnt and Maxlat RegisterCapabilityid Capability ID and Next Item Pointer RegisterRegister Capability ID and next item pointer NextitemRegister Power management capabilities Power Management Capabilities Register±14. Power Management Capabilities Register Description Power management extension Power Management Control and Status RegisterPower Management Extension Register Power management control and statusMiscellaneous configuration Miscellaneous Configuration Register±17. Miscellaneous Configuration Register Link enhancement control Link Enhancement Control Register±18. Link Enhancement Control Register Description Subdevid Subsystem Access RegisterSubsystem access ±19. Subsystem Access Register DescriptionGpio control Gpio Control Register±20. Gpio Control Register Description ±18 DMA Context Register Name Abbreviation Offset ±1. Ohci Register MapGuid ROM Guidrom Physical request filter low PhysicalRequestFilterLoSet IsoRecvIntEventClearIsochronous receive interrupt mask IsoRecvIntMaskSet PhysicalRequestFilterHiClearAsynchronous context control ContextControlSet Isochronous transmit context commandIsochronous receive context command CommandPtr 40Ch + 32*n Pointer Context match ContextMatchOhci version Ohci Version Register±2. Ohci Version Register Description RSU Guid ROM Register±3. Guid ROM Register Description Guid ROM±4. Asynchronous Transmit Retries Register Description Asynchronous Transmit Retries RegisterCSR Data Register Asynchronous transmit retriesCSR control CSR Compare RegisterCSR Control Register CSR compareBus Identification Register Configuration ROM Header RegisterConfiguration ROM header ±6. Configuration ROM Header Register DescriptionBus options Bus Options Register±7. Bus Options Register Description Guid low Guid High RegisterGuid Low Register Guid highPosted Write Address Low Register Configuration ROM Mapping RegisterConfiguration ROM mapping ±8. Configuration ROM Mapping Register DescriptionVendor ID Posted Write Address High RegisterPosted write address high ±9. Posted Write Address High Register DescriptionHost controller control Host Controller Control Register±10. Host Controller Control Register Description Self-ID count Self-ID Buffer Pointer RegisterSelf-ID Count Register Self ID-buffer pointerIsochronous receive channel mask high Isochronous Receive Channel Mask High RegisterIsochronous receive channel mask low Isochronous Receive Channel Mask Low RegisterInterrupt event Interrupt Event Register±14. Interrupt Event Register Description Arrq Rscu Arrs RscuRscu RSC Interrupt Mask RegisterInterrupt mask ±15. Interrupt Mask Register DescriptionIsochronous transmit interrupt event Isochronous Transmit Interrupt Event RegisterIsochronous transmit interrupt mask Isochronous Transmit Interrupt Mask RegisterIsochronous transmit interrupt mask ±21Isochronous receive interrupt mask Isochronous Receive Interrupt Event RegisterIsochronous Receive Interrupt Mask Register Isochronous receive interrupt eventFairness control Fairness Control RegisterFairness control ±18. Fairness Control Register DescriptionLink control Link Control Register±19. Link Control Register Description CPS Node Identification RegisterNode identification ±20. Node Identification Register DescriptionPHY layer control PHY Layer Control Register±21. PHY Control Register Description 24±12 Isochronous Cycle Timer RegisterIsochronous cycle timer ±22. Isochronous Cycle Timer Register DescriptionAsynchronous request filter high Asynchronous Request Filter High Register±23. Asynchronous Request Filter High Register Description ±29 ±30 Asynchronous Request Filter Low RegisterAsynchronous request filter low ±24. Asynchronous Request Filter Low Register DescriptionAre accepted Physical Request Filter High RegisterPhysical request filter high ±25. Physical Request Filter High Register Description±32 Physical request filter low Physical Request Filter Low RegisterPhysical request filter low ±26. Physical Request Filter Low Register Description±34 Physical Upper Bound Register Optional RegisterPhysical upper bound Physical upper boundRscu RSU Asynchronous Context Control RegisterAsynchronous context control ±27. Asynchronous Context Control Register DescriptionAsynchronous context command pointer Asynchronous Context Command Pointer Register31±4 DescriptorAddress Isochronous transmit context control Isochronous Transmit Context Control RegisterRSC RSU Isochronous receive context control Isochronous Transmit Context Command Pointer RegisterIsochronous transmit context command pointer Isochronous Receive Context Control RegisterMatch register see .43 is ignored CycleMatchEnableReserved. Bits 27±16 return 0s when read MultiChanMode±40 Isochronous Receive Context Command Pointer RegisterIsochronous receive context command pointer Isochronous receive context command pointer±31. Isochronous Receive Context Match Register Description When the command descriptor w field is set to 11bIsochronous Receive Context Match Register Isochronous receive context match±42 Gpio Interface Page ROM Offset OHCI/PCI Offset Register Bits Loaded From ROM ±1. Registers and Bits Loadable through Serial ROM13h PCI register 40h PCI Ohci register Byte Byte Description Address ±2. Serial ROM MapRsvd PME Absolute Maximum Ratings Over Operating Temperature Ranges² Electrical CharacteristicsOperation MIN NOM Recommended Operating ConditionsUnit Parameter Measured MIN TYP MAX Unit Switching Characteristics for PCI Interface§Switching Characteristics for PHY-Link Interface§ Operation Test MIN MAX Unit ConditionsPage PZ S-PQFP-G100 Mechanical InformationPage Important Notice

TSB12LV26 specifications

The Texas Instruments TSB12LV26 is a high-performance, low-voltage transceiver designed for Serial Bus applications. It is widely recognized for its robust features and versatility, making it a popular choice among engineers and designers in various industries. One of the primary features of the TSB12LV26 is its support for high-speed data transmission, enabling it to operate at speeds up to 400 Mbps. This capability is essential for applications that demand rapid data transfer, such as in multimedia and communication systems.

The TSB12LV26 is part of the IEEE 1394 standard, also known as FireWire, which is widely used for connecting devices like digital cameras, external hard drives, and printers. The chip operates within a voltage range of 2.7V to 3.6V, making it suitable for low-power applications where energy efficiency is critical. The integration of advanced Low-Voltage Differential Signaling (LVDS) technology within the TSB12LV26 enhances signal integrity and reduces electromagnetic interference, resulting in more reliable performance over longer distances.

In terms of its physical characteristics, the TSB12LV26 is available in a compact 48-pin HTQFP package, which is beneficial for space-constrained designs. The device features a comprehensive set of input and output pins, allowing for flexible connectivity options. Additionally, the TSB12LV26 includes advanced power management features, including low-power modes that help extend battery life in portable devices.

Another significant advantage of the TSB12LV26 is its capability for peer-to-peer communication, enabling devices to connect and communicate directly without the need for a central controller. This functionality supports a wide range of device configurations and simplifies system architecture. Furthermore, the transceiver offers built-in support for asynchronous and isochronous data transfer, making it adaptable for various application requirements.

The TSB12LV26 also adheres to stringent EMI and ESD protection standards, ensuring reliable operation in challenging environments. With a rich feature set, excellent performance characteristics, and compliance with industry standards, the Texas Instruments TSB12LV26 remains an ideal choice for engineers looking to implement high-speed and reliable communication in their designs. Overall, it represents a significant advancement in the field of data transmission technology, making it a preferred component for numerous electronic applications.
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