Texas Instruments TMS320DM646X DMSOC manual Asynchronous Write Operations Normal Mode

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2.5.4.2Asynchronous Write Operations (Normal Mode)

An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to asynchronous memory. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous write operation in Normal mode are described in Table 8 and an example timing diagram of a basic write operation is shown in Figure 5.

NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.

 

Table 8. Asynchronous Write Operation in Normal Mode

 

 

Time Interval

Pin Activity in WE Strobe Mode

 

 

Turnaround

Once the EMIF receives a write request, the EMIF waits for the programmed number of turn-around cycles

period

before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA

 

field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:

•If the current write operation was directly proceeded by another write operation to the same CS space, no turnaround cycles are inserted.

•If the current write operation was not directly proceeded by a write operation to the same CS space and the TA field has been cleared to 0, one turnaround cycle will be inserted.

After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.

Start of setup

At the beginning of the setup period:

period

• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values

 

 

 

in ACFGn.

 

• The address pins EM_A and EM_BA and the data pins EM_D become valid.

 

 

 

pin falls to indicate a write (if not already low from a previous operation).

 

• The EM_RW

 

•

 

falls to enable the external device (if not already low from a previous operation).

 

EM_CS

Start of strobe

At the beginning of the strobe period of a write operation:

period

 

 

 

 

 

 

 

• EM_WE falls

 

Start of hold

At the beginning of the hold period

period

 

 

 

 

 

 

 

• EM_WE rises

 

End of hold

At the end of the hold period:

period

• The address pins EM_A and EM_BA become invalid

 

 

• The data pins become invalid

 

 

 

 

 

pin rises (if no more operations are required to complete the current request)

 

• The EM_RW

 

•

 

 

rises (if no more operations are required to complete the current request)

 

EM_CS

 

The EMIF may be required to issue additional write operations to a device with a small data bus width in order to

 

complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another

 

operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this

 

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

 

asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the

 

turnaround period for the pending read or write operation.

 

 

 

 

 

 

 

 

16 Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralClock Control Functional Block DiagramEmif Requests Signal Descriptions Emif PinsPin Multiplexing Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrRead and Write Operations in Normal Mode Asynchronous Read Operations Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Read and Write Operations in Select Strobe Mode Asynchronous Read Operations Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Nand Flash Mode Configuring for Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashInterfacing to a Non-CE Dont Care Nand Flash Nand Flash Status Register NandfsrInterfacing to a TI DSP HPI Reset and Initialization Considerations Extended Wait Mode and the Emwait PinData Bus Parking Interrupt Support Emif InterruptInterrupt Events Interrupt Monitor and Control Bit FieldsPower Management Interrupt MultiplexingProgram Execution Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramAsram Output Timing Characteristics Meeting AC Timing Requirements for AsramEmif Input Timing Requirements Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Taking Into Account PCB Delays Asram Timing Requirements With PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Example Using TC5516100FT-12 Measured PCB Delays for TC5516100FT-12 ExampleEmif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Configuring A2CR for TC5516100FT-12 Example Interfacing to Nand FlashMargin Requirements Recommended MarginsEmif Read Timing Requirements Meeting AC Timing Requirements for Nand FlashNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Emif Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring A1CR for HY27UA081G1M Example Configuring Nandfcr for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Field Descriptions Revision Code and Status Register RcsrBit Field Value Description Asynchronous Wait Cycle Configuration Register Awccr WP3 WP2 WP1 WP0CS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Emif Interrupt Raw Register Eirr Field DescriptionsWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Emif Interrupt Mask Register Eimr Field DescriptionsWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Emif Interrupt Mask Set Register Eimsr Field DescriptionsWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Emif Interrupt Mask Clear Register Eimcr Field DescriptionsWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Nand Flash n ECC Registers NANDF1ECC-NANDF4ECCNand Flash Status Register Nandfsr Field Descriptions WaitstNand Flash n ECC Register NANDECCn Field Descriptions P8O P4O P2O P1OP8E P4E P2E P1E P8ODocument Revision History Additions/Modifications/DeletionsDSP Products ApplicationsRfid
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