Texas Instruments TMS320DM646X DMSOC manual Nand Read and Program Operations

Page 24

Architecture

www.ti.com

2.5.6.4NAND Read and Program Operations

A NAND Flash access cycle is composed of a command, address, and data phase. The EMIF will not automatically generate these three phases to complete a NAND access with one transfer request. To complete a NAND access cycle, multiple single asynchronous access cycles (as described above) must be completed by the EMIF. Software must be used to request the appropriate asynchronous accesses to complete a NAND Flash access cycle. This software must be developed to the specification of the chosen NAND Flash device.

Since NAND operations are divided into single asynchronous access cycles, the chip select signal will not remain activated for the duration of the NAND operation. Instead, the chip select signal will deactivate between each asynchronous access cycle. For this reason, the EMIF does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read. See Section 2.5.6.8 for workaround.

Care must be taken when performing a NAND read or write operation via the EDMA. See Section 2.5.6.5 for more details.

NOTE: The EMIF does not support NAND Flash devices that require the chip select signal to remain low during the tR time for a read. See Section 2.5.6.8 for workaround.

2.5.6.5NAND Data Read and Write via DMA

When performing NAND accesses, the EDMA is most efficiently used for the data phase of the access. The command and address phases of the NAND access require only a few words of data to be transferred and therefore do not take advantage of the EDMA'sability to transfer larger quantities of data with a single request. In this section we will focus on using the EDMA for the data phase of a NAND access.

There are two conditions that require care to be taken when performing NAND reads and writes via the EDMA. These are:

•CLE_EM_A[2] and ALE_EM_A[1] are lower address lines and must be driven low

•The EMIF does not support a constant address mode, but only supports linear incrementing address modes.

Since the EMIF does not support a constant addressing mode, when programming the EDMA, a linear incrementing address mode must be used. When using a linear incrementing address mode, since the CLE and ALE are driven by lower address lines, care must be taken not to increase the address into a range the drives CLE and/or ALE high. To prevent the address from incrementing into a range that drives CLE and/or ALE high, the EDMA ACNT, BCNT, SIDX, DIDX, and synchronization type must be programmed appropriately. The proper EDMA configurations are described below.

EDMA setup for a NAND Flash data read:

•ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)

•BCNT = transfer size in bytes/ACNT

•SIDX (source index) = 0

•DIDX (destination index) = ACNT

•AB synchronized

EDMA setup for a NAND Flash data write:

•ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)

•BCNT = transfer size in bytes/ACNT

•SIDX (source index) = ACNT

•DIDX (destination index) = 0

•AB synchronized

24

Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

 

Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Page 23 Page 25
Image 24
Page 23 Page 25
Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Clock ControlEmif Requests Signal Descriptions Emif PinsPin Multiplexing Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrRead and Write Operations in Normal Mode Asynchronous Read Operations Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Read and Write Operations in Select Strobe Mode Asynchronous Read Operations Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Nand Flash Mode Configuring for Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Support Emif InterruptInterrupt Events Interrupt Monitor and Control Bit FieldsPower Management Interrupt MultiplexingProgram Execution Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramAsram Output Timing Characteristics Meeting AC Timing Requirements for AsramEmif Input Timing Requirements Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Taking Into Account PCB Delays Asram Timing Requirements With PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Example Using TC5516100FT-12 Measured PCB Delays for TC5516100FT-12 ExampleEmif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Configuring A2CR for TC5516100FT-12 Example Interfacing to Nand FlashMargin Requirements Recommended MarginsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring A1CR for HY27UA081G1M Example Configuring Nandfcr for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description Asynchronous Wait Cycle Configuration Register Awccr WP3 WP2 WP1 WP0CS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Emif Interrupt Raw Register Eirr Field DescriptionsWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Emif Interrupt Mask Register Eimr Field DescriptionsWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Emif Interrupt Mask Set Register Eimsr Field DescriptionsWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Emif Interrupt Mask Clear Register Eimcr Field DescriptionsWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Nand Flash n ECC Registers NANDF1ECC-NANDF4ECCNand Flash Status Register Nandfsr Field Descriptions WaitstNand Flash n ECC Register NANDECCn Field Descriptions P8O P4O P2O P1OP8E P4E P2E P1E P8ODocument Revision History Additions/Modifications/DeletionsProducts Applications DSPRfid
Top Page Image Contents