Texas Instruments TMS320DM646X DMSOC Description of the Emif Interrupt Mask Set Register Eimsr

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Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued)

Parameter

Description

ASIZE

Asynchronous Device Bus Width.

 

This field determines the data bus width of the asynchronous interface in the following way:

 

• ASIZE = 0 selects an 8-bit bus

 

• ASIZE = 1 selects a 16-bit bus

 

The configuration of ASIZE determines the function of the EM_A and EM_BA pins as described in

 

Section 2.5.1. This field also determines the number of external accesses required to fulfill a request

 

generated by one of the sources mentioned in Section 2.2. For example, a request for a 32-bit word

 

would require four external access when ASIZE = 0h. Refer to the datasheet of the external

 

asynchronous device to determine the appropriate setting for this field.

 

 

Table 4. Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)

Parameter

Description

WPn

WAIT Polarity.

 

• WPn = 0 selects active-low polarity

 

• WPn = 1 selects active-high polarity

 

When set to 1, the EMIF will wait if the EM_WAITn pin is high. When cleared to 0, the EMIF will wait if the

 

EM_WAITn pin is low. The EMIF must have the Extended Wait mode enabled (EW bit in the asynchronous

 

configuration register (ACFGn) is set to 1) for the EM_WAITn pin to affect the width of the strobe period.

 

 

MEWC

Maximum Extended Wait Cycles.

 

This field configures the number of EMIF clock cycles the EMIF will wait for the EM_WAITn pin to be deactivated

 

during the strobe period of an access cycle. The maximum number of EMIF clock cycles the EMIF will wait is

 

determined by the following formula:

 

Maximum Extended Wait Cycles = (MEWC + 1) × 16

 

If the EM_WAITn pin is not deactivated within the time specified by this field, the EMIF resumes the access cycle,

 

registering whatever data is on the bus and preceding to the hold period of the access cycle. This situation is

 

referred to as an asynchronous timeout. An asynchronous timeout generates an interrupt if it has been enabled in

 

the EMIF interrupt mask set register (EIMSR). Refer to Section 2.5.11 for more information about the EMIF

 

interrupts.

 

 

Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR)

Parameter Description

WRMSETn Wait Rise Mask Set.

Writing a 1 enables an interrupt to be generated when a rising edge on EM_WAITn occurs.

ATMSET Asynchronous Timeout Mask Set.

Writing a 1 to this bit enables an interrupt to be generated when an asynchronous timeout occurs.

Table 6. Description of the EMIF Interrupt Mast Clear Register (EIMCR)

Parameter Description

WRMCLRn Wait Rise Mask Clear.

Writing a 1 to this bit disables the interrupt, clearing the WRMSETn bit in the EMIF interrupt mask set register (EIMSR).

ATMCLR Asynchronous Timeout Mask Clear.

Writing a 1 to this bit disables the interrupt, clearing the ATMSET bit in the EMIF interrupt mask set register (EIMSR).

SPRUEQ7C –February 2010

Asynchronous External Memory Interface (EMIF) 13

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Copyright © 2010, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesClock Control Functional Block DiagramEmif Requests Emif Pins Signal DescriptionsPin Multiplexing Asynchronous Controller and InterfaceEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrAsynchronous Read Operations Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Asynchronous Read Operations Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Configuring for Nand Flash Mode Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationInterfacing to a Non-CE Dont Care Nand Flash Nand Flash Status Register NandfsrInterfacing to a TI DSP HPI Reset and Initialization Considerations Extended Wait Mode and the Emwait PinData Bus Parking Emif Interrupt Interrupt SupportInterrupt Events Interrupt Monitor and Control Bit FieldsInterrupt Multiplexing Power ManagementProgram Execution Emulation ConsiderationsInterfacing to Asynchronous Sram Asram Connecting to AsramMeeting AC Timing Requirements for Asram Asram Output Timing CharacteristicsEmif Input Timing Requirements Asram Input Timing Requirement for a ReadAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Asram Timing Requirements With PCB Delays Taking Into Account PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Measured PCB Delays for TC5516100FT-12 Example Example Using TC5516100FT-12Emif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Interfacing to Nand Flash Configuring A2CR for TC5516100FT-12 ExampleMargin Requirements Recommended MarginsEmif Read Timing Requirements Meeting AC Timing Requirements for Nand FlashNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Emif Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring Nandfcr for HY27UA081G1M Example Configuring A1CR for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectOffset Acronym Register Description External Memory Interface Emif RegistersRevision Code and Status Register Rcsr Field Descriptions Revision Code and Status Register RcsrBit Field Value Description WP3 WP2 WP1 WP0 Asynchronous Wait Cycle Configuration Register AwccrCS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Field Descriptions Emif Interrupt Raw Register EirrWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Field Descriptions Emif Interrupt Mask Register EimrWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Field Descriptions Emif Interrupt Mask Set Register EimsrWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Field Descriptions Emif Interrupt Mask Clear Register EimcrWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register NandfsrNand Flash Status Register Nandfsr Field Descriptions WaitstP8O P4O P2O P1O Nand Flash n ECC Register NANDECCn Field DescriptionsP8E P4E P2E P1E P8OAdditions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid
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