Texas Instruments TMS320DM646X DMSOC manual Configuring for Nand Flash Mode

Page 22

Architecture

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2.5.6NAND Flash Mode

NAND Flash mode is the EMIF'sthird mode of operation. Each chip select space may be placed in NAND Flash mode individually by setting the appropriate CSnNAND bit in the NAND Flash control register (NANDFCR). Table 11 displays the bit fields present in NANDFCR and briefly describes their use.

When a chip select space is configured to operate in NAND Flash mode, the EMIF hardware can calculate the error correction code (ECC) for each 512 byte data transfer to that chip select space. The EMIF hardware will not generate the NAND access cycle, which includes the command, address, and data phases, necessary to complete a transfer to NAND Flash. All NAND Flash operations can be divided into single asynchronous cycles and with the help of software, the EMIF can execute a complete NAND access cycle.

Table 11. Description of the NAND Flash Control Register (NANDFCR)

Parameter Description

CS5ECC NAND Flash ECC state for chip select 5.

•Set to 1 to start an ECC calculation.

•Cleared to 0 when NAND Flash 4 ECC register (NANDF4ECC) is read.

CS4ECC NAND Flash ECC state for chip select 4.

•Set to 1 to start an ECC calculation.

•Cleared to 0 when NAND Flash 3 ECC register (NANDF3ECC) is read.

CS3ECC NAND Flash ECC state for chip select 3.

•Set to 1 to start an ECC calculation.

•Cleared to 0 when NAND Flash 2 ECC register (NANDF2ECC) is read.

CS2ECC NAND Flash ECC state for chip select 2.

•Set to 1 to start an ECC calculation.

•Cleared to 0 when NAND Flash 1 ECC register (NANDF1ECC) is read.

CS5NAND NAND Flash mode for chip select 5.

• Set to 1 to enable NAND Flash mode.

CS4NAND NAND Flash mode for chip select 4.

• Set to 1 to enable NAND Flash mode.

CS3NAND NAND Flash mode for chip select 3.

• Set to 1 to enable NAND Flash mode.

CS2NAND NAND Flash mode for chip select 2.

•Set to 1 to enable NAND Flash mode.

2.5.6.1Configuring for NAND Flash Mode

Similar to the asynchronous accesses previously described, the EMIF'smemory-mapped registers must be programmed appropriately to interface to a NAND Flash device. Table 12 lists the bit fields that must be programmed when operating in NAND Flash mode and the values to set each bit. NAND Flash mode cannot be used with Extended Wait mode.

Table 12. Configuration For NAND Flash

Register

Bit Field

Configuration Value

Asynchronous configuration

SS

0

register (ACFGn)

EW

0

 

 

W_SETUP/R_SETUP

See Section 3.2 for information on how to program.

 

W_STROBE/R_STROBE

See Section 3.2 for information on how to program.

 

W_HOLD/R_HOLD

See Section 3.2 for information on how to program.

 

ASIZE

Programmed to equal the width of the NAND Flash device

 

 

 

NAND Flash control register

CS2NAND

1

(NANDFCR)

22 Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralClock Control Functional Block DiagramEmif Requests Pin Multiplexing Signal DescriptionsEmif Pins Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrAsynchronous Read Operation in Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Asynchronous Read Operation in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Configuration For Nand Flash Nand Flash ModeConfiguring for Nand Flash Mode Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashInterfacing to a Non-CE Dont Care Nand Flash Nand Flash Status Register NandfsrInterfacing to a TI DSP HPI Reset and Initialization Considerations Extended Wait Mode and the Emwait PinData Bus Parking Interrupt Events Interrupt SupportEmif Interrupt Interrupt Monitor and Control Bit FieldsProgram Execution Power ManagementInterrupt Multiplexing Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramEmif Input Timing Requirements Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Parameter Description Read Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Emif Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Margin Requirements Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Recommended MarginsEmif Read Timing Requirements Meeting AC Timing Requirements for Nand FlashNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Emif Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Parameter Setting Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Field Descriptions Revision Code and Status Register RcsrBit Field Value Description CS5WAIT CS4WAIT CS3WAIT CS2WAIT Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 WR2 WR1 WR0 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3WRM3 WRM2 WRM1 WRM0 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3AT bit in the Emif interrupt raw register Eirr WRMSET3 WRMSET2 WRMSET1 WRMSET0 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3Bit in Eimcr WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Field Descriptions Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC WaitstP8E P4E P2E P1E Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8ODocument Revision History Additions/Modifications/DeletionsDSP Products ApplicationsRfid
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