Texas Instruments TMS320DM646X DMSOC manual Read and Write Operations in Normal Mode

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2.5.4Read and Write Operations in Normal Mode

Normal mode is the asynchronous interface'sdefault mode of operation. The Normal mode is selected when the SS bit in the asynchronous configuration register (ACFGn) is cleared to 0. In this mode, the EM_CS signal operates as a chip enable signal, active throughout the duration of the memory access.

2.5.4.1Asynchronous Read Operations (Normal Mode)

An asynchronous read is performed when any of the requesters mentioned in Section 2.2 request a read from the attached asynchronous memory. In the event that the read request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous read operation in Normal mode are described in Table 7 and an example timing diagram of a basic read operation is shown in Figure 4.

NOTE: During the entirety of an asynchronous read operation, the WRITE_WE and EM_RW pins are driven high.

 

Table 7. Asynchronous Read Operation in Normal Mode

 

 

Time Interval

Pin Activity in WE Strobe Mode

 

 

Turnaround

Once the EMIF receives a read request, the EMIF waits for the programmed number of turn-around cycles

period

before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA

 

field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:

•If the current read operation was directly proceeded by another read operation to the same CS space, no turnaround cycles are inserted.

•If the current read operation was not directly proceeded by a read operation to the same CS space and the TA field has been cleared to 0, one turn-around cycle will be inserted.

After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.

Start of setup

At the beginning of the setup period:

period

• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values

 

 

 

in ACFGn.

 

• The address pins EM_A and EM_BA become valid

 

•

 

falls to enable the external device (if not already low from a previous operation)

 

EM_CS

Start of strobe

At the beginning of the strobe period

period

 

 

 

 

• READ_OE falls

 

Start of hold

At the beginning of the hold period:

period

 

 

 

 

• READ_OE rises

 

 

• The EMIF samples the data on the EM_D bus.

 

 

 

End of hold

At the end of the hold period:

period

• The address pins EM_A and EM_BA become invalid

 

 

•

 

rises (if no more operations are required to complete the current request)

 

EM_CS

 

The EMIF will be required to issue additional read operations to a device with a small data bus width in order to

 

complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another

 

operation without incurring the turn-round cycle delay. The setup, strobe, and hold values are not updated in this

 

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

 

asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF

 

instead enters directly into the turnaround period for the pending read or write operation.

 

 

 

 

 

14 Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralEmif Requests Functional Block DiagramClock Control Pin Multiplexing Signal DescriptionsEmif Pins Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrAsynchronous Read Operation in Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Asynchronous Read Operation in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Configuration For Nand Flash Nand Flash ModeConfiguring for Nand Flash Mode Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashInterfacing to a TI DSP HPI Nand Flash Status Register NandfsrInterfacing to a Non-CE Dont Care Nand Flash Data Bus Parking Extended Wait Mode and the Emwait PinReset and Initialization Considerations Interrupt Events Interrupt SupportEmif Interrupt Interrupt Monitor and Control Bit FieldsProgram Execution Power ManagementInterrupt Multiplexing Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramEmif Input Timing Requirements Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Parameter Description Read Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Emif Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Margin Requirements Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Recommended MarginsNand Flash Read Timing Requirements Meeting AC Timing Requirements for Nand FlashEmif Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Nand Flash Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MEmif Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Parameter Setting Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionBit Field Value Description Revision Code and Status Register RcsrRevision Code and Status Register Rcsr Field Descriptions CS5WAIT CS4WAIT CS3WAIT CS2WAIT Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 WR2 WR1 WR0 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3WRM3 WRM2 WRM1 WRM0 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3AT bit in the Emif interrupt raw register Eirr WRMSET3 WRMSET2 WRMSET1 WRMSET0 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3Bit in Eimcr WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Field Descriptions Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC WaitstP8E P4E P2E P1E Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8ODocument Revision History Additions/Modifications/DeletionsRfid Products ApplicationsDSP
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