Texas Instruments TMS320DM646X DMSOC manual Meeting AC Timing Requirements for Nand Flash

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3.2.2Meeting AC Timing Requirements for NAND Flash

When configuring the EMIF to interface to NAND Flash, you must consider the AC timing requirements of the NAND Flash as well as the AC timing requirements of the EMIF. These can be found in the data sheet for each respective device. The read and write asynchronous cycles are programmed separately in the asynchronous configuration register (ACFGn).

As described in Section 2.5.6, a NAND Flash access cycle is composed of a command, address, and data phases. The EMIF will not automatically generate these three phases to complete a NAND access with one transfer request. To complete a NAND access cycle, multiple single asynchronous access cycles must be completed by the EMIF. The command and address phases of a NAND Flash access cycle are asynchronous writes performed by the EMIF where as the data phase can be either an asynchronous write or a read depending on whether the NAND Flash is being programmed or read.

Therefore, to determine the required EMIF configuration to interface to the NAND Flash for a read operation, Table 25 and Table 26 list the AC timing parameters that must be considered.

	Table 25. EMIF Read Timing Requirements

Parameter	Description

tSU	Data Setup time, data valid before				high
			EM_OE
tH	Data Hold time, data valid after			high
		EM_OE

	Table 26. NAND Flash Read Timing Requirements

Parameter	Description

tRP	Read Pulse width
tREA	Read Enable Access time
tCEA	Chip Enable low to output valid
tCHZ	Chip Enable high to output High-impedance
tRC	Read Cycle time
tRHZ	Read enable high to output High-impedance
tCLR	Command Latch low to Read enable low

Figure 16 shows an asynchronous read access and describes how the EMIF and NAND Flash AC timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.

40	Asynchronous External Memory Interface (EMIF)	SPRUEQ7C –February 2010
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralClock Control Functional Block DiagramEmif Requests Signal Descriptions Emif PinsPin Multiplexing Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrRead and Write Operations in Normal Mode Asynchronous Read Operations Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Read and Write Operations in Select Strobe Mode Asynchronous Read Operations Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Nand Flash Mode Configuring for Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashInterfacing to a Non-CE Dont Care Nand Flash Nand Flash Status Register NandfsrInterfacing to a TI DSP HPI Reset and Initialization Considerations Extended Wait Mode and the Emwait PinData Bus Parking Interrupt Support Emif InterruptInterrupt Events Interrupt Monitor and Control Bit FieldsPower Management Interrupt MultiplexingProgram Execution Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramAsram Output Timing Characteristics Meeting AC Timing Requirements for AsramEmif Input Timing Requirements Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Taking Into Account PCB Delays Asram Timing Requirements With PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Example Using TC5516100FT-12 Measured PCB Delays for TC5516100FT-12 ExampleEmif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Configuring A2CR for TC5516100FT-12 Example Interfacing to Nand FlashMargin Requirements Recommended MarginsEmif Read Timing Requirements Meeting AC Timing Requirements for Nand FlashNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Emif Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring A1CR for HY27UA081G1M Example Configuring Nandfcr for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Field Descriptions Revision Code and Status Register RcsrBit Field Value Description Asynchronous Wait Cycle Configuration Register Awccr WP3 WP2 WP1 WP0CS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Emif Interrupt Raw Register Eirr Field DescriptionsWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Emif Interrupt Mask Register Eimr Field DescriptionsWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Emif Interrupt Mask Set Register Eimsr Field DescriptionsWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Emif Interrupt Mask Clear Register Eimcr Field DescriptionsWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Nand Flash n ECC Registers NANDF1ECC-NANDF4ECCNand Flash Status Register Nandfsr Field Descriptions WaitstNand Flash n ECC Register NANDECCn Field Descriptions P8O P4O P2O P1OP8E P4E P2E P1E P8ODocument Revision History Additions/Modifications/DeletionsDSP Products ApplicationsRfid