Texas Instruments TMS320DM646X DMSOC manual Signal Descriptions, Pin Multiplexing, Emif Pins

Page 10

Architecture

www.ti.com

2.3Signal Descriptions

Table 1 describes the function of each of the EMIF pins.

 

 

 

 

 

 

 

 

Table 1. EMIF Pins

 

 

 

 

 

Pins(s)

I/O

Description

 

 

 

 

 

EM_ A[22:0]

O

EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address that is

 

 

 

 

 

 

 

 

sent to the device.

 

EM_BA[1:0]

O

EMIF bank address. These pins are used in conjunction with the EM_A pins to form the address that is

 

 

 

 

 

 

 

 

sent to the device.

 

 

 

O

Active-low chip enable pin for asynchronous devices. These pins are meant to be connected to the

 

EM_CS[5:2]

 

 

 

 

 

 

 

 

chip-select pin of the attached asynchronous device.

 

EM_D[15:0]

I/O

EMIF data bus.

 

 

 

 

 

O

Read/Write select pin. This pin is high for the duration of an asynchronous read access cycle and low

 

EM_RW

 

 

 

 

 

 

 

 

for the duration of an asynchronous write cycle.

 

 

 

 

 

 

O

Active-low pin enable for asynchronous devices. This pin provides a signal which is active-low during

 

EM_OE

 

 

 

 

 

 

 

 

the strobe period of an asynchronous read access cycle.

 

 

 

 

 

 

 

O

Active-low write enable. This pin provides a signal which is active-low during the strobe period of an

 

EM_WE

 

 

 

 

 

 

 

 

asynchronous write access cycle.

 

EM_WAIT[5:2]

I

Wait input with programmable polarity. A connected asynchronous device can extend the strobe period

 

 

 

 

 

 

 

 

of an access cycle by asserting the WAIT input to the EMIF as described in Section 2.5.8. To enable

 

 

 

 

 

 

 

 

this functionality, the EW bit in the asynchronous configuration register (ACFGn) must be set to 1. In

 

 

 

 

 

 

 

 

addition, the WPn bit in the asynchronous wait cycle configuration register (AWCCR) must be

 

 

 

 

 

 

 

 

configured to define the polarity of the EM_WAITn pin.

 

 

 

 

 

 

 

 

 

2.4Pin Multiplexing

The EMIF pins are multiplexed with other peripherals such as PCI, HPI, GPIO, and ATA. See the device-specific data manual for instructions on how to select the EMIF pins for proper operation.

2.5Asynchronous Controller and Interface

The EMIF easily interfaces to a variety of asynchronous devices including Flash and ASRAM. It can be operated in three major modes:

•Normal mode

•Select Strobe (SS) mode

•NAND Flash mode

The behavior of the EM_CS signal is the single difference between Normal mode and Select Strobe mode (see Table 2). In Normal mode, the EM_CS signal becomes active at the beginning of the setup period and remains active for the duration of the transfer. In Select Strobe mode, the EM_CS signal functions as a strobe signal, active only during the strobe period of an access.

In NAND Flash mode, the EMIF hardware is able to calculate the error correction code (ECC) for each 512 byte data transfer. In addition to the three modes of operation, the EMIF also provides configurable cycle timing parameters and an Extended Wait mode that allows the connected device to extend the strobe period of an access cycle. The following sections describe the features related to interfacing with external asynchronous devices.

Table 2. Behavior of EM_CS Signal Between Normal Mode and

Select Strobe Mode

 

 

 

 

Mode

Operation of EM_CS[5:2]

Normal

Active during the entire asynchronous access cycle

Select Strobe

Active only during the strobe period of an access cycle

 

 

 

 

10

Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

 

Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Page 9 Page 11
Image 10
Page 9 Page 11
Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralClock Control Functional Block DiagramEmif Requests Pin Multiplexing Signal DescriptionsEmif Pins Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrAsynchronous Read Operation in Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Asynchronous Read Operation in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Configuration For Nand Flash Nand Flash ModeConfiguring for Nand Flash Mode Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashInterfacing to a Non-CE Dont Care Nand Flash Nand Flash Status Register NandfsrInterfacing to a TI DSP HPI Reset and Initialization Considerations Extended Wait Mode and the Emwait PinData Bus Parking Interrupt Events Interrupt SupportEmif Interrupt Interrupt Monitor and Control Bit FieldsProgram Execution Power ManagementInterrupt Multiplexing Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramEmif Input Timing Requirements Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Parameter Description Read Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Emif Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Margin Requirements Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Recommended MarginsEmif Read Timing Requirements Meeting AC Timing Requirements for Nand FlashNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Emif Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Parameter Setting Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Field Descriptions Revision Code and Status Register RcsrBit Field Value Description CS5WAIT CS4WAIT CS3WAIT CS2WAIT Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 WR2 WR1 WR0 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3WRM3 WRM2 WRM1 WRM0 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3AT bit in the Emif interrupt raw register Eirr WRMSET3 WRMSET2 WRMSET1 WRMSET0 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3Bit in Eimcr WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Field Descriptions Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC WaitstP8E P4E P2E P1E Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8ODocument Revision History Additions/Modifications/DeletionsDSP Products ApplicationsRfid
Top Page Image Contents