Texas Instruments TMS320DM646X DMSOC manual Emif Interrupt Raw Register Eirr, WR3 WR2 WR1 WR0

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Registers

4.4EMIF Interrupt Raw Register (EIRR)

The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-generated interrupts. The bits in EIRR are set when an interrupt condition occurs, regardless of the status of the EMIF interrupt mask set register (EIMSR) and EMIF interrupt mask clear register (EIMCR). Writing a 1 to a bit clears the bit and the corresponding bit in the EMIF interrupt mask register (EIMR). The EIRR is shown in Figure 23 and described in Table 36.

 

 

Figure 23. EMIF Interrupt Raw Register (EIRR)

 

 

31

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

 

 

 

15

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

R-0

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

Reserved

WR3

WR2

 

WR1

WR0

Reserved

AT

 

 

 

 

 

 

 

 

 

 

R-0

R/W1C-0

R/W1C-0

 

R/W1C-0

R/W1C-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

Table 36. EMIF Interrupt Raw Register (EIRR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

 

 

31-6

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

 

value of 0.

 

 

 

 

 

 

5

WR3

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[5] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[5] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[5] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM3 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

4

WR2

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[4] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[4] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[4] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM2 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

3

WR1

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[3] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[3] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[3] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM1 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

2

WR0

 

Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[0] pin has

 

 

 

 

occurred.

 

 

 

0

Indicates that a rising edge has not occurred on the EM_WAIT[0] pin. Writing a 0 has no effect.

 

 

 

1

Indicates that a rising edge has occurred on the EM_WAIT[0] pin. Writing a 1 will clear this bit and the

 

 

 

 

WRM0 bit in the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

1

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

 

value of 0.

 

 

 

 

 

 

0

AT

 

Asynchronous Timeout. This bit is set to 1 by hardware to indicate that during an extended

 

 

 

 

asynchronous memory access cycle the EM_WAITn pin did not go inactive within the number of cycles

 

 

 

defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR).

 

 

 

0

Indicates that an asynchronous timeout has not occurred. Writing a 0 has no effect.

 

 

 

1

Indicates that an asynchronous timeout has occurred. Writing a 1 will clear this bit and the ATM bit in

 

 

 

 

the EMIF interrupt mask register (EIMR).

 

 

 

 

 

 

 

 

 

 

 

SPRUEQ7C –February 2010

Asynchronous External Memory Interface (EMIF)

53

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Copyright © 2010, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesEmif Requests Functional Block DiagramClock Control Emif Pins Signal DescriptionsPin Multiplexing Asynchronous Controller and InterfaceEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrAsynchronous Read Operations Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Asynchronous Read Operations Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Configuring for Nand Flash Mode Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationInterfacing to a TI DSP HPI Nand Flash Status Register NandfsrInterfacing to a Non-CE Dont Care Nand Flash Data Bus Parking Extended Wait Mode and the Emwait PinReset and Initialization Considerations Emif Interrupt Interrupt SupportInterrupt Events Interrupt Monitor and Control Bit FieldsInterrupt Multiplexing Power ManagementProgram Execution Emulation ConsiderationsInterfacing to Asynchronous Sram Asram Connecting to AsramMeeting AC Timing Requirements for Asram Asram Output Timing CharacteristicsEmif Input Timing Requirements Asram Input Timing Requirement for a ReadAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Asram Timing Requirements With PCB Delays Taking Into Account PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Measured PCB Delays for TC5516100FT-12 Example Example Using TC5516100FT-12Emif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Interfacing to Nand Flash Configuring A2CR for TC5516100FT-12 ExampleMargin Requirements Recommended MarginsNand Flash Read Timing Requirements Meeting AC Timing Requirements for Nand FlashEmif Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Nand Flash Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MEmif Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring Nandfcr for HY27UA081G1M Example Configuring A1CR for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectOffset Acronym Register Description External Memory Interface Emif RegistersBit Field Value Description Revision Code and Status Register RcsrRevision Code and Status Register Rcsr Field Descriptions WP3 WP2 WP1 WP0 Asynchronous Wait Cycle Configuration Register AwccrCS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Field Descriptions Emif Interrupt Raw Register EirrWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Field Descriptions Emif Interrupt Mask Register EimrWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Field Descriptions Emif Interrupt Mask Set Register EimsrWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Field Descriptions Emif Interrupt Mask Clear Register EimcrWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register NandfsrNand Flash Status Register Nandfsr Field Descriptions WaitstP8O P4O P2O P1O Nand Flash n ECC Register NANDECCn Field DescriptionsP8E P4E P2E P1E P8OAdditions/Modifications/Deletions Document Revision HistoryRfid Products ApplicationsDSP
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