Texas Instruments TMS320DM646X DMSOC manual Nand Flash Write Timing Requirements

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To determine the required EMIF configuration to interface to the NAND Flash for a write operation, Table 27 lists the NAND AC timing parameters for a command latch, address latch, and data input latch that must be considered.

		Table 27. NAND Flash Write Timing Requirements

Parameter	Description

tWP	Write Pulse width
tCLS	CLE Setup time
tALS	ALE Setup time
tCS		Setup time
	CS
tDS	Data Setup time
tCLH	CLE Hold time
tALH	ALE Hold time
tCH		Hold time
	CS
tDH	Data Hold time
tWC	Write Cycle time

Figure 17 to Figure 19 show the command latch, address latch, and data input latch of the NAND access.

From Figure 17 to Figure 19, the following equations may be derived. tcyc is the period at which the EMIF operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to W_SETUP width in EMIF clock cycles minus 1 cycle.

W_SETUP w maxtCLS(m) , tALS(m) , tCS(m)* 1

tcyctcyc tcyc

W_STROBE w tWP(m) * 1

tcyc

W_SETUP ) W_STROBE w tDS(m) * 1

tcyc

W_HOLD w maxtCLH(m) , tALH(m) , tCH(m) , tDH(m)* 1

tcyctcyc tcyc tcyc

W_SETUP ) W_STROBE ) W_HOLD w tWC(m) * 3

tcyc

42	Asynchronous External Memory Interface (EMIF)	SPRUEQ7C –February 2010
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Clock ControlEmif Requests Pin Multiplexing Signal DescriptionsEmif Pins Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrAsynchronous Read Operation in Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Asynchronous Read Operation in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Configuration For Nand Flash Nand Flash ModeConfiguring for Nand Flash Mode Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Events Interrupt SupportEmif Interrupt Interrupt Monitor and Control Bit FieldsProgram Execution Power ManagementInterrupt Multiplexing Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramEmif Input Timing Requirements Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Parameter Description Read Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Emif Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Margin Requirements Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Recommended MarginsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Parameter Setting Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description CS5WAIT CS4WAIT CS3WAIT CS2WAIT Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 WR2 WR1 WR0 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3WRM3 WRM2 WRM1 WRM0 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3AT bit in the Emif interrupt raw register Eirr WRMSET3 WRMSET2 WRMSET1 WRMSET0 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3Bit in Eimcr WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Field Descriptions Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC WaitstP8E P4E P2E P1E Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8ODocument Revision History Additions/Modifications/DeletionsProducts Applications DSPRfid