Texas Instruments TMS320DM646X DMSOC manual Emif Interrupt Mask Set Register Eimsr, WRMSET3

Page 56

Registers

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4.6EMIF Interrupt Mask Set Register (EIMSR)

The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit is set to 1, the corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the associated interrupt condition occurs. If a bit is cleared to 0, the the corresponding bit in EIMR will always read 0 and no interrupts are generated when the associated interrupt condition occurs. Writing a 1 to the WRMSETn and ATMSET bits enables each respective interrupt. The EIMSR is shown in Figure 25 and described in Table 38.

 

 

Figure 25. EMIF Interrupt Mask Set Register (EIMSR)

 

 

31

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

 

15

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

 

7

6

5

4

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

Reserved

WRMSET3

WRMSET2

 

WRMSET1

WRMSET0

 

Reserved

ATMSET

 

R-0

R/W1S-0

R/W1S-0

 

R/W1S-0

R/W1S-0

R-0

R/W1S-0

LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing 0 has no effect); -n= value after reset

Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-6

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

5

WRMSET3

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR3 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR3 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR3 bit in

 

 

 

EIMCR.

 

 

 

 

4

WRMSET2

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR2 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR2 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR2 bit in

 

 

 

EIMCR.

 

 

 

 

3

WRMSET1

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR1 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR1 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR1 bit in

 

 

 

EIMCR.

 

 

 

 

2

WRMSET0

 

Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the

 

 

 

WRMCLR0 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To

 

 

 

clear this bit, a 1 must be written to the WRMCLR0 bit in EIMCR.

 

 

0

Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.

 

 

1

Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR0 bit in

 

 

 

EIMCR.

 

 

 

 

1

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

56

Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralEmif Requests Functional Block DiagramClock Control Signal Descriptions Emif PinsPin Multiplexing Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrRead and Write Operations in Normal Mode Asynchronous Read Operations Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Read and Write Operations in Select Strobe Mode Asynchronous Read Operations Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Nand Flash Mode Configuring for Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashInterfacing to a TI DSP HPI Nand Flash Status Register NandfsrInterfacing to a Non-CE Dont Care Nand Flash Data Bus Parking Extended Wait Mode and the Emwait PinReset and Initialization Considerations Interrupt Support Emif InterruptInterrupt Events Interrupt Monitor and Control Bit FieldsPower Management Interrupt MultiplexingProgram Execution Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramAsram Output Timing Characteristics Meeting AC Timing Requirements for AsramEmif Input Timing Requirements Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Taking Into Account PCB Delays Asram Timing Requirements With PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Example Using TC5516100FT-12 Measured PCB Delays for TC5516100FT-12 ExampleEmif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Configuring A2CR for TC5516100FT-12 Example Interfacing to Nand FlashMargin Requirements Recommended MarginsNand Flash Read Timing Requirements Meeting AC Timing Requirements for Nand FlashEmif Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Nand Flash Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MEmif Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring A1CR for HY27UA081G1M Example Configuring Nandfcr for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionBit Field Value Description Revision Code and Status Register RcsrRevision Code and Status Register Rcsr Field Descriptions Asynchronous Wait Cycle Configuration Register Awccr WP3 WP2 WP1 WP0CS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Emif Interrupt Raw Register Eirr Field DescriptionsWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Emif Interrupt Mask Register Eimr Field DescriptionsWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Emif Interrupt Mask Set Register Eimsr Field DescriptionsWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Emif Interrupt Mask Clear Register Eimcr Field DescriptionsWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Nand Flash n ECC Registers NANDF1ECC-NANDF4ECCNand Flash Status Register Nandfsr Field Descriptions WaitstNand Flash n ECC Register NANDECCn Field Descriptions P8O P4O P2O P1OP8E P4E P2E P1E P8ODocument Revision History Additions/Modifications/DeletionsRfid Products ApplicationsDSP
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