Texas Instruments TMS320DM646X DMSOC manual ECC Generation, ECC Value for 8-Bit Nand Flash

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Architecture

2.5.6.6ECC Generation

If the CSnNAND bit in the NAND Flash control register (NANDFCR) is set to 1, the EMIF supports ECC calculation for up to 512 bytes for the corresponding chip select care. To perform the ECC calculation, the CS2ECC bit in NANDFCR must be set to 1. The ECC calculation for each chip select space is independent of each other. It is the responsibility of the software to start the ECC calculation by writing to the CS2ECC bit prior to issuing a write or read to NAND Flash. It is also the responsibility of the software to read the calculated ECC from the NAND Flash 1 ECC register (NANDF1ECC) once the transfer to NAND Flash has completed. If the software writes or reads more than 512 bytes, the ECC will be incorrect. There is a NANDECCn for each chip select space and when read, the corresponding CSnECC bit in NANDFCR is cleared. The NANDF1ECC is cleared upon writing a 1 to the CS2ECC bit. Figure 9 shows the algorithm used to calculate the ECC value for an 8-bit NAND Flash.

For an 8-bit NAND Flash p1e through p4e are column parities and p8e through p2048 are row parities. Similarly, the algorithm can be extended to a 16-bit NAND Flash. For a 16-bit NAND Flash p1e through p8e are column parities and p16e through p2048 are row parities. The software must ignore the unwanted parity bits if ECC is desired for less than 512 bytes of data. For example. p2048e and p2048o are not required for ECC on 256 bytes of data. Similarly, p1024e, p1024o, p2048e, and p2048o are not required for ECC on 128 bytes of data.

Figure 9. ECC Value for 8-Bit NAND Flash

Byte 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8e

p16e

Byte 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8o

p32e

Byte 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8e

p16o

Byte 4

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

p8o

Byte 1	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0	p8e
Byte 2	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0	p16e
									p8o
Byte 3	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0	p32o
									p8e
Byte 4	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0	p16o
									p8o
	p1o	p1e	p1o	p1e	p1o	p1e	p1o	p1e
	p2o		p2e		p2o		p2e
		p4o				p4e

p2048e

p2048o

SPRUEQ7C –February 2010	Asynchronous External Memory Interface (EMIF)	25
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesClock Control Functional Block DiagramEmif Requests Emif Pins Signal DescriptionsPin Multiplexing Asynchronous Controller and InterfaceEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrAsynchronous Read Operations Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Asynchronous Read Operations Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Configuring for Nand Flash Mode Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationInterfacing to a Non-CE Dont Care Nand Flash Nand Flash Status Register NandfsrInterfacing to a TI DSP HPI Reset and Initialization Considerations Extended Wait Mode and the Emwait PinData Bus Parking Emif Interrupt Interrupt SupportInterrupt Events Interrupt Monitor and Control Bit FieldsInterrupt Multiplexing Power ManagementProgram Execution Emulation ConsiderationsInterfacing to Asynchronous Sram Asram Connecting to AsramMeeting AC Timing Requirements for Asram Asram Output Timing CharacteristicsEmif Input Timing Requirements Asram Input Timing Requirement for a ReadAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Asram Timing Requirements With PCB Delays Taking Into Account PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Measured PCB Delays for TC5516100FT-12 Example Example Using TC5516100FT-12Emif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Interfacing to Nand Flash Configuring A2CR for TC5516100FT-12 ExampleMargin Requirements Recommended MarginsEmif Read Timing Requirements Meeting AC Timing Requirements for Nand FlashNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Emif Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring Nandfcr for HY27UA081G1M Example Configuring A1CR for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectOffset Acronym Register Description External Memory Interface Emif RegistersRevision Code and Status Register Rcsr Field Descriptions Revision Code and Status Register RcsrBit Field Value Description WP3 WP2 WP1 WP0 Asynchronous Wait Cycle Configuration Register AwccrCS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Field Descriptions Emif Interrupt Raw Register EirrWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Field Descriptions Emif Interrupt Mask Register EimrWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Field Descriptions Emif Interrupt Mask Set Register EimsrWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Field Descriptions Emif Interrupt Mask Clear Register EimcrWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register NandfsrNand Flash Status Register Nandfsr Field Descriptions WaitstP8O P4O P2O P1O Nand Flash n ECC Register NANDECCn Field DescriptionsP8E P4E P2E P1E P8OAdditions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid