Texas Instruments TMS320DM646X DMSOC manual External Memory Interface Emif Registers

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Registers

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4Registers

The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers (MMRs). Table 32 lists the memory-mapped registers for the EMIF. See the device-specific data manual for the memory address of these registers. All other register offset addresses not listed in Table 32 should be considered as reserved locations and the register contents should not be modified.

NOTE: The EMIF MMRs only support word (4 byte) accesses. Performing a byte (8 bit) or halfword (16 bit) write to a register results in unknown behavior.

Table 32. External Memory Interface (EMIF) Registers

Offset	Acronym	Register Description	Section
0	RCSR	Revision Code and Status Register	Section 4.1
4h	AWCCR	Asynchronous Wait Cycle Configuration Register	Section 4.2
10h	A1CR	Asynchronous 1 Configuration Register (CS2 space)	Section 4.3
14h	A2CR	Asynchronous 2 Configuration Register (CS3 space)	Section 4.3
18h	A3CR	Asynchronous 3 Configuration Register (CS4 space)	Section 4.3
1Ch	A4CR	Asynchronous 4 Configuration Register (CS5 space)	Section 4.3
40h	EIRR	EMIF Interrupt Raw Register	Section 4.4
44h	EIMR	EMIF Interrupt Mask Register	Section 4.5
48h	EIMSR	EMIF Interrupt Mask Set Register	Section 4.6
4Ch	EIMCR	EMIF Interrupt Mask Clear Register	Section 4.7
60h	NANDFCR	NAND Flash Control Register	Section 4.8
64h	NANDFSR	NAND Flash Status Register	Section 4.9
70h	NANDF1ECC	NAND Flash 1 ECC Register (CS2 Space)	Section 4.10
74h	NANDF2ECC	NAND Flash 2 ECC Register (CS3 Space)	Section 4.10
78h	NANDF3ECC	NAND Flash 3 ECC Register (CS4 Space)	Section 4.10
7Ch	NANDF4ECC	NAND Flash 4 ECC Register (CS5 Space)	Section 4.10

48	Asynchronous External Memory Interface (EMIF)	SPRUEQ7C –February 2010
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Clock ControlEmif Requests Signal Descriptions Emif PinsPin Multiplexing Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrRead and Write Operations in Normal Mode Asynchronous Read Operations Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Read and Write Operations in Select Strobe Mode Asynchronous Read Operations Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Nand Flash Mode Configuring for Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Support Emif InterruptInterrupt Events Interrupt Monitor and Control Bit FieldsPower Management Interrupt MultiplexingProgram Execution Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramAsram Output Timing Characteristics Meeting AC Timing Requirements for AsramEmif Input Timing Requirements Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Taking Into Account PCB Delays Asram Timing Requirements With PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Example Using TC5516100FT-12 Measured PCB Delays for TC5516100FT-12 ExampleEmif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Configuring A2CR for TC5516100FT-12 Example Interfacing to Nand FlashMargin Requirements Recommended MarginsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring A1CR for HY27UA081G1M Example Configuring Nandfcr for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description Asynchronous Wait Cycle Configuration Register Awccr WP3 WP2 WP1 WP0CS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Emif Interrupt Raw Register Eirr Field DescriptionsWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Emif Interrupt Mask Register Eimr Field DescriptionsWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Emif Interrupt Mask Set Register Eimsr Field DescriptionsWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Emif Interrupt Mask Clear Register Eimcr Field DescriptionsWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Nand Flash n ECC Registers NANDF1ECC-NANDF4ECCNand Flash Status Register Nandfsr Field Descriptions WaitstNand Flash n ECC Register NANDECCn Field Descriptions P8O P4O P2O P1OP8E P4E P2E P1E P8ODocument Revision History Additions/Modifications/DeletionsProducts Applications DSPRfid