Texas Instruments TMS320DM646X DMSOC manual Emif Interrupt Mask Register Eimr, WRM3 WRM2 WRM1 WRM0

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Registers

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4.5EMIF Interrupt Mask Register (EIMR)

Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used to monitor and clear the status of the EMIF’s hardware-generated interrupts. The main difference between the two registers is that when the bits in EIMR are set, an active-high pulse is sent to the CPU interrupt controller. Also, the bits in EIMR are only set to 1, if the associated interrupt has been enabled in the EMIF interrupt mask set register (EIMSR). The EIMR is shown in Figure 24 and described in Table 37.

 

 

Figure 24. EMIF Interrupt Mask Register (EIMR)

 

 

31

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

R-0

 

 

 

 

15

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

R-0

 

 

 

 

7

6

5

4

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

Reserved

WRM3

WRM2

 

WRM1

WRM0

 

Reserved

ATM

 

 

 

 

 

 

 

 

 

 

 

R-0

R/W1C-0

R/W1C-0

 

R/W1C-0

R/W1C-0

R-0

R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

31-6

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

5

WRM3

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[5] pin, provided that the WRMSET3 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM3 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

4

WRM2

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[4] pin, provided that the WRMSET2 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM2 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

3

WRM1

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[3] pin, provided that the WRMSET1 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM1 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

2

WRM0

 

Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the

 

 

 

EM_WAIT[2] pin, provided that the WRMSET0 bit is set to 1 in the EMIF interrupt mask set register

 

 

 

(EIMSR).

 

 

0

Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.

 

 

1

Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM0 bit in

 

 

 

the EMIF interrupt raw register (EIRR).

 

 

 

 

1

Reserved

0

Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default

 

 

 

value of 0.

 

 

 

 

54

Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Clock ControlEmif Requests Pin Multiplexing Signal DescriptionsEmif Pins Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrAsynchronous Read Operation in Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Asynchronous Read Operation in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Configuration For Nand Flash Nand Flash ModeConfiguring for Nand Flash Mode Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Events Interrupt SupportEmif Interrupt Interrupt Monitor and Control Bit FieldsProgram Execution Power ManagementInterrupt Multiplexing Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramEmif Input Timing Requirements Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Parameter Description Read Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Emif Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Margin Requirements Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Recommended MarginsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Parameter Setting Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description CS5WAIT CS4WAIT CS3WAIT CS2WAIT Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 WR2 WR1 WR0 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3WRM3 WRM2 WRM1 WRM0 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3AT bit in the Emif interrupt raw register Eirr WRMSET3 WRMSET2 WRMSET1 WRMSET0 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3Bit in Eimcr WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Field Descriptions Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC WaitstP8E P4E P2E P1E Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8ODocument Revision History Additions/Modifications/DeletionsProducts Applications DSPRfid
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