Texas Instruments TMS320DM646X DMSOC manual Read This First

Page 6

Preface

SPRUEQ7C – February 2010

Read This First

About This Manual

This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices.

Notational Conventions

This document uses the following conventions.

•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

•Registers in this document are shown in figures and described in tables.

–Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

–Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM646x DMSoC, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUEP8 — TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signal processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRUEP9 — TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARM subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP subsystem and a majority of the peripherals and external memories.

SPRUEQ0 — TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

6

Preface

SPRUEQ7C –February 2010

 

 

Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Page 5 Page 7
Image 6
Page 5 Page 7
Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Clock ControlEmif Requests Pin Multiplexing Signal DescriptionsEmif Pins Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrAsynchronous Read Operation in Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Asynchronous Read Operation in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Configuration For Nand Flash Nand Flash ModeConfiguring for Nand Flash Mode Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Events Interrupt SupportEmif Interrupt Interrupt Monitor and Control Bit FieldsProgram Execution Power ManagementInterrupt Multiplexing Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramEmif Input Timing Requirements Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Parameter Description Read Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Emif Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Margin Requirements Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Recommended MarginsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Parameter Setting Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description CS5WAIT CS4WAIT CS3WAIT CS2WAIT Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 WR2 WR1 WR0 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3WRM3 WRM2 WRM1 WRM0 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3AT bit in the Emif interrupt raw register Eirr WRMSET3 WRMSET2 WRMSET1 WRMSET0 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3Bit in Eimcr WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Field Descriptions Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC WaitstP8E P4E P2E P1E Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8ODocument Revision History Additions/Modifications/DeletionsProducts Applications DSPRfid
Top Page Image Contents