Texas Instruments TMS320DM646X DMSOC Meeting AC Timing Requirements for Asram, Read Cycle time

Page 31

www.ti.com

Use Cases

3.1.2Meeting AC Timing Requirements for ASRAM

When configuring the EMIF to interface to ASRAM, you must consider the AC timing requirements of the ASRAM as well as the AC timing requirements of the EMIF. These can be found in the data sheet for each respective device. The read and write asynchronous cycles are programmed separately in the asynchronous configuration register (ACFGn).

For a read access, Table 15 to Table 17 list the AC timing specifications that must be considered.

 

Table 15. EMIF Input Timing Requirements

 

 

Parameter

Description

 

 

 

 

tSU

Data Setup time, data valid before

 

 

high

EM_OE

tH

Data Hold time, data valid after

 

 

high

EM_OE

 

Table 16. ASRAM Output Timing Characteristics

 

 

Parameter

Description

 

 

tACC

Address Access time

tOH

Output data Hold time for address change

tCOD

Output Disable time from chip enable

 

Table 17. ASRAM Input Timing Requirement for a Read

 

 

Parameter

Description

 

 

tRC

Read Cycle time

Figure 12 shows an asynchronous read access and describes how the EMIF and ASRAM AC timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.

From Figure 12, the following equations may be derived. tcyc is the period at which the EMIF operates. The R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data sheet specifications are typically given in nano seconds. This explains the presence of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to R_SETUP width in EMIF clock cycles minus 1 cycle.

R_SETUP ) R_STROBE w ￿tACC(m) ) tSU￿ * 1

tcyc

R_SETUP ) R_STROBE ) R_HOLD w tRC(m) * 3

tcyc

R_HOLD w ￿tH * tOH(m)￿ * 1

tcyc

The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write cycles. This parameter protects against the situation when the output turn-off time of the memory is longer than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same time as the memory, causing contention on the bus. By examining Figure 12, the equation for TA can be derived as:

TA w tCOD(m) * 1

tcyc

SPRUEQ7C –February 2010

Asynchronous External Memory Interface (EMIF)

31

Submit Documentation Feedback

 

 

Copyright © 2010, Texas Instruments Incorporated

Page 30 Page 32
Image 31
Page 30 Page 32
Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesClock Control Functional Block DiagramEmif Requests Asynchronous Controller and Interface Signal DescriptionsEmif Pins Pin MultiplexingEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrTime Interval Pin Activity in WE Strobe Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Asynchronous Read Operation in Normal ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Time Interval Pin Activity in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Asynchronous Read Operation in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Description of the Nand Flash Control Register Nandfcr Nand Flash ModeConfiguring for Nand Flash Mode Configuration For Nand FlashDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationInterfacing to a Non-CE Dont Care Nand Flash Nand Flash Status Register NandfsrInterfacing to a TI DSP HPI Reset and Initialization Considerations Extended Wait Mode and the Emwait PinData Bus Parking Interrupt Monitor and Control Bit Fields Interrupt SupportEmif Interrupt Interrupt EventsEmulation Considerations Power ManagementInterrupt Multiplexing Program ExecutionInterfacing to Asynchronous Sram Asram Connecting to AsramAsram Input Timing Requirement for a Read Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Emif Input Timing RequirementsAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Write Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Parameter Description Read AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Asram Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Emif Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Recommended Margins Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Margin RequirementsEmif Read Timing Requirements Meeting AC Timing Requirements for Nand FlashNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Emif Timing Requirements for HY27UA081G1M Example Example Using Hynix HY27UA081G1MNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Nand Flash mode for chip select Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Parameter SettingOffset Acronym Register Description External Memory Interface Emif RegistersRevision Code and Status Register Rcsr Field Descriptions Revision Code and Status Register RcsrBit Field Value Description WP3 Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 CS5WAIT CS4WAIT CS3WAIT CS2WAITEMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3 WR2 WR1 WR0WRM3 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3 WRM2 WRM1 WRM0AT bit in the Emif interrupt raw register Eirr WRMSET3 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3 WRMSET2 WRMSET1 WRMSET0Bit in Eimcr WRMCLR3 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrWaitst Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register Nandfsr Field DescriptionsP8O Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8E P4E P2E P1EAdditions/Modifications/Deletions Document Revision HistoryDSP Products ApplicationsRfid
Top Page Image Contents