Texas Instruments TMS320DM646X DMSOC Extended Wait Mode and the Emwait Pin, Data Bus Parking

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Architecture

2.5.8Extended Wait Mode and the EM_WAIT Pin

The Extended Wait mode is a mode in which the external asynchronous device may assert control over the length of the strobe period. The Extended Wait mode can be entered by setting the EW bit in the asynchronous configuration register (ACFGn). When the EW bit is set, the EMIF monitors the EM_WAIT[5:2] pins to determine if the attached device wishes to extend the strobe period of the current access cycle beyond the programmed number of clock cycles.

When the EMIF detects that the EM_WAIT pin has been asserted, it will begin inserting extra strobe cycles into the operation until the EM_WAIT pin is deactivated by the external device. The EMIF will then return to the last cycle of the programmed strobe period and the operation will proceed as usual from this point. Refer to the device-specific data manual for details on the timing requirements of the EM_WAIT signal.

The EM_WAIT pin cannot be used to extend the strobe period indefinitely. The programmable MEWC bit in the asynchronous wait cycle configuration register (AWCCR) determines the maximum number of EMIF clock cycles the strobe period may be extended beyond the programmed length. When the number of cycles programmed in the MEWC bit expires, the EMIF proceeds to the hold period of the operation regardless of the state of the EM_WAIT pin. The EMIF can also generate an interrupt upon expiration of this counter. See Section 2.5.11.1 for details on enabling this interrupt.

For the EMIF to function properly in the Extended Wait mode, the WPn bit in AWCCR must be programmed to match the polarity of the attached device. When the WPn bit is in its reset state of 1, the EMIF will insert wait cycles when the EM_WAITn pin is sampled high; when the WPn bit is cleared to 0, the EMIF will insert wait cycles only when the EM_WAITn pin is sampled low. This programmability allows for a glueless connection to larger variety of asynchronous devices.

Finally, a restriction is placed on the setup and strobe period timing parameters when operating in Extended Wait mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than 4, and the sum of the R_SETUP and R_STROBE fields must be greater than 4 for the EMIF to recognize the EM_WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in ACFGn.

2.5.9Data Bus Parking

The EMIF always drives the data bus to the previous write data value when it is idle. This feature is called data bus parking. Only when the EMIF issues a read command to the external memory does it stop driving the data bus. After the EMIF latches the last read data, it immediately parks the data bus again.

2.5.10Reset and Initialization Considerations

The EMIF and its registers will be reset when any of the following events occur:

1.The RESET pin on the device is asserted

2.The EMIF is placed in reset by the Power and Sleep Controller.

When a reset occurs, the EMIF will immediately abandon any access request that is in progress and reset all registers and internal logic to their default state.

Following device power up and deassertion of the RESET pin, the internal clock to the EMIF is turned on and the EMIF memory-mapped registers are programmed to their default values.

SPRUEQ7C –February 2010

Asynchronous External Memory Interface (EMIF)

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesFunctional Block Diagram Clock ControlEmif Requests Asynchronous Controller and Interface Signal DescriptionsEmif Pins Pin MultiplexingEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrTime Interval Pin Activity in WE Strobe Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Asynchronous Read Operation in Normal ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Time Interval Pin Activity in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Asynchronous Read Operation in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Description of the Nand Flash Control Register Nandfcr Nand Flash ModeConfiguring for Nand Flash Mode Configuration For Nand FlashDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Monitor and Control Bit Fields Interrupt SupportEmif Interrupt Interrupt EventsEmulation Considerations Power ManagementInterrupt Multiplexing Program ExecutionInterfacing to Asynchronous Sram Asram Connecting to AsramAsram Input Timing Requirement for a Read Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Emif Input Timing RequirementsAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Write Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Parameter Description Read AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Asram Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Emif Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Recommended Margins Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Margin RequirementsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Nand Flash mode for chip select Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Parameter SettingOffset Acronym Register Description External Memory Interface Emif RegistersRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description WP3 Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 CS5WAIT CS4WAIT CS3WAIT CS2WAITEMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3 WR2 WR1 WR0WRM3 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3 WRM2 WRM1 WRM0AT bit in the Emif interrupt raw register Eirr WRMSET3 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3 WRMSET2 WRMSET1 WRMSET0Bit in Eimcr WRMCLR3 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrWaitst Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register Nandfsr Field DescriptionsP8O Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8E P4E P2E P1EAdditions/Modifications/Deletions Document Revision HistoryProducts Applications DSPRfid
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