Texas Instruments TMS320DM646X DMSOC manual Interfacing to Nand Flash, Margin Requirements

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Use Cases

Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields are equal to EMIF clock cycles minus 1 cycle, the A2CR should be configured as in Table 23. In this example, the EM_WAIT signal is not implemented; therefore, the asynchronous wait cycle configuration register (AWCCR) does not need to be programmed.

Table 23. Configuring A2CR for TC5516100FT-12 Example

Parameter	Setting

SS	Select Strobe mode.
	• SS = 0. Places EMIF in Normal Mode.

EW	Extended Wait mode enable.
	• EW = 0. Disabled Extended wait mode.

W_SETUP/R_SETUP	Read/Write setup widths.
	•	W_SETUP = 0
	•	R_SETUP = 0

W_STROBE/R_STROBE	Read/Write strobe widths.
	•	W_STROBE = 0
	•	R_STROBE = 0

W_HOLD/R_HOLD	Read/Write hold widths.
	•	W_HOLD = 0
	•	R_HOLD = 0

TA	Minimum turnaround time.
	•	TA = 0

ASIZE	Asynchronous Device Bus Width.
	• ASIZE = 1, select a 16-bit data bus width

3.2Interfacing to NAND Flash

The following example explains how to interface the EMIF to the Hynix HY27UA081G1M NAND Flash device. Section 2.5.6.2 describes how to connect the EMIF to the HY27UA081G1M.

3.2.1Margin Requirements

The Flash interface is typically a low-performance interface compared to synchronous memory interfaces, high-speed asynchronous memory interfaces, and high-speed FIFO interfaces. For this reason, this example gives little attention to minimizing the amount of margin required when programming the asynchronous timing parameters. The approach used requires approximately 10 ns of margin on all parameters, which is not significant for a 100-ns read or write cycle. For additional details on minimizing the amount of margin, see the ASRAM example given in Section 3.1.

	Table 24. Recommended Margins

Timing Parameter	Recommended Margin

Output Setup	10 nS
Output Hold	10 nS
Input Setup	10 nS
Input Hold	10 nS

SPRUEQ7C –February 2010	Asynchronous External Memory Interface (EMIF)	39
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesFunctional Block Diagram Clock ControlEmif Requests Asynchronous Controller and Interface Signal DescriptionsEmif Pins Pin MultiplexingEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrTime Interval Pin Activity in WE Strobe Mode Read and Write Operations in Normal ModeAsynchronous Read Operations Normal Mode Asynchronous Read Operation in Normal ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Time Interval Pin Activity in Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operations Select Strobe Mode Asynchronous Read Operation in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Description of the Nand Flash Control Register Nandfcr Nand Flash ModeConfiguring for Nand Flash Mode Configuration For Nand FlashDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Monitor and Control Bit Fields Interrupt SupportEmif Interrupt Interrupt EventsEmulation Considerations Power ManagementInterrupt Multiplexing Program ExecutionInterfacing to Asynchronous Sram Asram Connecting to AsramAsram Input Timing Requirement for a Read Asram Output Timing CharacteristicsMeeting AC Timing Requirements for Asram Emif Input Timing RequirementsAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Write Access Taking Into Account PCB DelaysAsram Timing Requirements With PCB Delays Parameter Description Read AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Asram Timing Requirements for TC5516100FT-12 Example Example Using TC5516100FT-12Measured PCB Delays for TC5516100FT-12 Example Emif Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Recommended Margins Configuring A2CR for TC5516100FT-12 ExampleInterfacing to Nand Flash Margin RequirementsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Nand Flash mode for chip select Configuring A1CR for HY27UA081G1M ExampleConfiguring Nandfcr for HY27UA081G1M Example Parameter SettingOffset Acronym Register Description External Memory Interface Emif RegistersRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description WP3 Asynchronous Wait Cycle Configuration Register AwccrWP3 WP2 WP1 WP0 CS5WAIT CS4WAIT CS3WAIT CS2WAITEMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR WR3 Emif Interrupt Raw Register EirrEmif Interrupt Raw Register Eirr Field Descriptions WR3 WR2 WR1 WR0WRM3 Emif Interrupt Mask Register EimrEmif Interrupt Mask Register Eimr Field Descriptions WRM3 WRM2 WRM1 WRM0AT bit in the Emif interrupt raw register Eirr WRMSET3 Emif Interrupt Mask Set Register EimsrEmif Interrupt Mask Set Register Eimsr Field Descriptions WRMSET3 WRMSET2 WRMSET1 WRMSET0Bit in Eimcr WRMCLR3 Emif Interrupt Mask Clear Register EimcrEmif Interrupt Mask Clear Register Eimcr Field Descriptions WRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrWaitst Nand Flash Status Register NandfsrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register Nandfsr Field DescriptionsP8O Nand Flash n ECC Register NANDECCn Field DescriptionsP8O P4O P2O P1O P8E P4E P2E P1EAdditions/Modifications/Deletions Document Revision HistoryProducts Applications DSPRfid