Texas Instruments TMS320DM646X DMSOC manual Programmable Asynchronous Parameters

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2.5.2Programmable Asynchronous Parameters

The EMIF allows a high degree of programmability for shaping asynchronous accesses. The programmable parameters are:

•Setup: The time between the beginning of a memory cycle (address valid) and the activation of the output enable or write enable strobe

•Strobe: The time between the activation and deactivation of output enable or write enable strobe.

•Hold: The time between the deactivation of output enable or write enable strobe and the end of the cycle, which may be indicated by an address change or the deactivation of the EM_CS signal.

Separate parameters are provided for read and write cycles. Each parameter is programmed in terms of EMIF clock cycles.

2.5.3Configuring the EMIF for Asynchronous Accesses

The operation of the EMIF'sasynchronous interface can be configured by programming the appropriate memory-mapped registers. The reset value and bit position for each register field can be found in Section 4. The following tables list the programmable register fields and describe the purpose of each field. These registers should not be programmed while an asynchronous access is in progress. The transfer following a write to these registers will use the new configuration.

Table 3 describes the asynchronous configuration register (ACFGn). There are four ACFGns. Each chip select space has a dedicated ACFGn. This allows each chip select space to be programmed independently to interface to different asynchronous memory types.

 

Table 3. Description of the Asynchronous Configuration Register (ACFGn)

 

 

 

 

 

 

 

 

 

Parameter

Description

 

 

 

 

 

 

 

 

 

SS

Select Strobe mode. This bit selects the EMIF's mode of operation in the following way:

 

 

• SS = 0 selects Normal mode.

 

is active for duration of access.

 

 

EM_CS

 

 

• SS = 1 selects Select Strobe mode.

 

 

acts as a strobe.

 

 

 

 

 

 

 

EM_CS

 

 

 

 

 

 

EW

Extended Wait mode enable.

 

 

 

 

 

 

 

• EW = 0 disables Extended Wait mode

 

 

 

 

 

 

 

• EW = 1 enables Extended Wait mode

 

 

 

 

 

 

 

When set to 1, the EMIF enables its Extended Wait mode in which the strobe width of an access

 

 

cycle can be extended in response to the assertion of the EM_WAIT[5:2] pins. The WPn bit in the

 

 

asynchronous wait cycle configuration register (AWCCR) controls the polarity of the EM_WAITn pin.

 

 

See Section 2.5.8 for more details on this mode of operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W_SETUP/R_SETUP

Read/Write setup widths.

 

 

 

 

 

 

 

These fields define the number of EMIF clock cycles of setup time for the address pins (EM_A and

 

 

EM_BA) and asynchronous chip enable

(EM_CS)

 

before the read strobe pin

(READ_OE)

or write

 

 

strobe pin

(WRITE_WE)

falls, minus 1 cycle. For writes, the W_SETUP field also defines the setup

 

 

time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to

 

 

determine the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W_STROBE/R_STROBE

Read/Write strobe widths.

 

 

 

 

 

 

 

These fields define the number of EMIF clock cycles between the falling and rising of the read strobe

 

 

pin

 

or write strobe pin

 

 

 

 

 

 

 

 

 

(READ_OE)

(WRITE_WE), minus 1 cycle. If Extended Wait mode is enabled

 

 

by setting the EW bit in the asynchronous configuration register (ACFGn), these fields must be set to

 

 

a value greater than zero. Refer to the datasheet of the external asynchronous device to determine

 

 

the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W_HOLD/R_HOLD

Read/Write hold widths.

 

 

 

 

 

 

 

These fields define the number of EMIF clock cycles of hold time for the address pins (EM_A and

 

 

EM_BA) and asynchronous chip enable

(EM_CS)

 

after the read strobe pin

(READ_OE)

or write

 

 

strobe pin

(WRITE_WE)

rises, minus 1 cycle. For writes, the W_HOLD field also defines the hold

 

 

time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to

 

 

determine the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TA

Minimum turnaround time.

 

 

 

 

 

 

 

This field defines the minimum number of EMIF clock cycles between the end of one asynchronous

 

 

access and the start of another, minus 1 cycle. This delay is not incurred when a read is followed by

 

 

a read, or a write is followed by a write to the same chip select space. The purpose of this feature is

 

 

to avoid contention on the bus. Refer to the datasheet of the external asynchronous device to

 

 

determine the appropriate setting for this field.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12 Asynchronous External Memory Interface (EMIF)

SPRUEQ7C –February 2010

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Related Documentation From Texas Instruments Features Purpose of the PeripheralFunctional Block Diagram Clock ControlEmif Requests Signal Descriptions Emif PinsPin Multiplexing Asynchronous Controller and InterfaceInterfacing to Asynchronous Memory Emif Asynchronous InterfaceConfiguring the Emif for Asynchronous Accesses Programmable Asynchronous ParametersDescription of the Emif Interrupt Mask Set Register Eimsr Description of the Emif Interrupt Mast Clear Register EimcrRead and Write Operations in Normal Mode Asynchronous Read Operations Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operations Normal Mode Asynchronous Write Operation in Normal ModeAddress Read and Write Operations in Select Strobe Mode Asynchronous Read Operations Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operations Select Strobe Mode Asynchronous Write Operation in Select Strobe ModeEMD Nand Flash Mode Configuring for Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrConnecting to Nand Flash Driving CLE and ALENand Read and Program Operations Nand Data Read and Write via DMAECC Generation ECC Value for 8-Bit Nand FlashNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Interrupt Support Emif InterruptInterrupt Events Interrupt Monitor and Control Bit FieldsPower Management Interrupt MultiplexingProgram Execution Emulation ConsiderationsConnecting to Asram Interfacing to Asynchronous Sram AsramAsram Output Timing Characteristics Meeting AC Timing Requirements for AsramEmif Input Timing Requirements Asram Input Timing Requirement for a ReadTiming Waveform of an Asram Read Asram Input Timing Requirements for a WriteTiming Waveform of an Asram Write Taking Into Account PCB Delays Asram Timing Requirements With PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Example Using TC5516100FT-12 Measured PCB Delays for TC5516100FT-12 ExampleEmif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Configuring A2CR for TC5516100FT-12 Example Interfacing to Nand FlashMargin Requirements Recommended MarginsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring A1CR for HY27UA081G1M Example Configuring Nandfcr for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectExternal Memory Interface Emif Registers Offset Acronym Register DescriptionRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description Asynchronous Wait Cycle Configuration Register Awccr WP3 WP2 WP1 WP0CS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Emif Interrupt Raw Register Eirr Field DescriptionsWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Emif Interrupt Mask Register Eimr Field DescriptionsWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Emif Interrupt Mask Set Register Eimsr Field DescriptionsWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Emif Interrupt Mask Clear Register Eimcr Field DescriptionsWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Nand Flash Control Register Nandfcr Field DescriptionsNand Flash Status Register Nandfsr Nand Flash n ECC Registers NANDF1ECC-NANDF4ECCNand Flash Status Register Nandfsr Field Descriptions WaitstNand Flash n ECC Register NANDECCn Field Descriptions P8O P4O P2O P1OP8E P4E P2E P1E P8ODocument Revision History Additions/Modifications/DeletionsProducts Applications DSPRfid
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