Texas Instruments TMS320DM646X DMSOC manual Functional Block Diagram, Clock Control, Emif Requests

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Architecture

1.3Functional Block Diagram

Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external EMIF pins. Section 2.2 contains a description of the entities internal to the device that can send requests to the EMIF, along with their prioritization. Section 2.3 describes the EMIF'sexternal pins and summarizes their purpose when interfacing with SDRAM and asynchronous devices.

Figure 1. EMIF Functional Block Diagram

VICP

DSP

ARM

EDMA3

SCR

EMIF

EM_CS[5:2] EM_OE EM_RW

EM_WAIT[5:2]

EM_WE EM_BA[1:0] EM_D[15:0] EM_A[22:0]

Master peripherals

2Architecture

This section provides details about the architecture and operation of the EMIF.

2.1Clock Control

The EMIF'sinternal clock is sourced from the SYSCLK3 clock domain of PLL controller 0 and cannot be sourced directly from an external input clock. The frequency of the SYSCLK3 clock domain is the PLL0 frequency divided by 4. Changes to the frequency of the input clock to PLL controller 0 and to the PLL controller 0 multiplier values alters the operating frequency of the EMIF. See the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9) for more information on how to program the PLL controller.

2.2EMIF Requests

Four different sources within the device can make requests to the EMIF. These requests consist of accesses to asynchronous memory and EMIF memory-mapped registers. Because the EMIF can process only one request at a time, a high performance switched central resource (SCR) exists to provide prioritized requests from the different sources to the EMIF. Each requester has a programmable priority value that may be configured in the System Module MSTPRI0 register or in the EDMACC QUEPRI register. See the device-specific data manual for more information.

If a request is submitted from two or more sources simultaneously, the SCR will forward the highest priority request to the EMIF first. Upon completion of a request, the SCR again evaluates the pending requests and forwards the highest priority pending request to the EMIF.

SPRUEQ7C –February 2010	Asynchronous External Memory Interface (EMIF)	9
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Related Documentation From Texas Instruments Purpose of the Peripheral FeaturesFunctional Block Diagram Clock ControlEmif Requests Emif Pins Signal DescriptionsPin Multiplexing Asynchronous Controller and InterfaceEmif Asynchronous Interface Interfacing to Asynchronous MemoryProgrammable Asynchronous Parameters Configuring the Emif for Asynchronous AccessesDescription of the Emif Interrupt Mast Clear Register Eimcr Description of the Emif Interrupt Mask Set Register EimsrAsynchronous Read Operations Normal Mode Read and Write Operations in Normal ModeAsynchronous Read Operation in Normal Mode Time Interval Pin Activity in WE Strobe ModeTiming Waveform of an Asynchronous Read Cycle in Normal Mode Asynchronous Write Operation in Normal Mode Asynchronous Write Operations Normal ModeAddress Asynchronous Read Operations Select Strobe Mode Read and Write Operations in Select Strobe ModeAsynchronous Read Operation in Select Strobe Mode Time Interval Pin Activity in Select Strobe ModeEMD Data Asynchronous Write Operation in Select Strobe Mode Asynchronous Write Operations Select Strobe ModeEMD Configuring for Nand Flash Mode Nand Flash ModeConfiguration For Nand Flash Description of the Nand Flash Control Register NandfcrDriving CLE and ALE Connecting to Nand FlashNand Data Read and Write via DMA Nand Read and Program OperationsECC Value for 8-Bit Nand Flash ECC GenerationNand Flash Status Register Nandfsr Interfacing to a Non-CE Dont Care Nand FlashInterfacing to a TI DSP HPI Extended Wait Mode and the Emwait Pin Reset and Initialization ConsiderationsData Bus Parking Emif Interrupt Interrupt SupportInterrupt Events Interrupt Monitor and Control Bit FieldsInterrupt Multiplexing Power ManagementProgram Execution Emulation ConsiderationsInterfacing to Asynchronous Sram Asram Connecting to AsramMeeting AC Timing Requirements for Asram Asram Output Timing CharacteristicsEmif Input Timing Requirements Asram Input Timing Requirement for a ReadAsram Input Timing Requirements for a Write Timing Waveform of an Asram ReadTiming Waveform of an Asram Write Asram Timing Requirements With PCB Delays Taking Into Account PCB DelaysParameter Description Read Access Write AccessTiming Waveform of an Asram Read with PCB Delays Timing Waveform of an Asram Write with PCB Delays Measured PCB Delays for TC5516100FT-12 Example Example Using TC5516100FT-12Emif Timing Requirements for TC5516100FT-12 Example Asram Timing Requirements for TC5516100FT-12 Example27 12 5 Rsetup Rstrobe w Interfacing to Nand Flash Configuring A2CR for TC5516100FT-12 ExampleMargin Requirements Recommended MarginsMeeting AC Timing Requirements for Nand Flash Emif Read Timing RequirementsNand Flash Read Timing Requirements Timing Waveform of a Nand Flash Read Nand Flash Write Timing Requirements Timing Waveform of a Nand Flash Command Write Timing Waveform of a Nand Flash Data Write Example Using Hynix HY27UA081G1M Emif Timing Requirements for HY27UA081G1M ExampleNand Flash Timing Requirements for HY27UA081G1M Example Rstrobe w max 1 w Configuring Nandfcr for HY27UA081G1M Example Configuring A1CR for HY27UA081G1M ExampleParameter Setting Nand Flash mode for chip selectOffset Acronym Register Description External Memory Interface Emif RegistersRevision Code and Status Register Rcsr Revision Code and Status Register Rcsr Field DescriptionsBit Field Value Description WP3 WP2 WP1 WP0 Asynchronous Wait Cycle Configuration Register AwccrCS5WAIT CS4WAIT CS3WAIT CS2WAIT WP3EMWAIT2 pin is used Asynchronous n Configuration Registers A1CR-A4CR Emif Interrupt Raw Register Eirr Field Descriptions Emif Interrupt Raw Register EirrWR3 WR2 WR1 WR0 WR3Emif Interrupt Mask Register Eimr Field Descriptions Emif Interrupt Mask Register EimrWRM3 WRM2 WRM1 WRM0 WRM3AT bit in the Emif interrupt raw register Eirr Emif Interrupt Mask Set Register Eimsr Field Descriptions Emif Interrupt Mask Set Register EimsrWRMSET3 WRMSET2 WRMSET1 WRMSET0 WRMSET3Bit in Eimcr Emif Interrupt Mask Clear Register Eimcr Field Descriptions Emif Interrupt Mask Clear Register EimcrWRMCLR3 WRMCLR2 WRMCLR1 WRMCLR0 WRMCLR3Written to the Atmset bit in Eimsr Nand Flash Control Register Nandfcr Field Descriptions Nand Flash Control Register NandfcrNand Flash n ECC Registers NANDF1ECC-NANDF4ECC Nand Flash Status Register NandfsrNand Flash Status Register Nandfsr Field Descriptions WaitstP8O P4O P2O P1O Nand Flash n ECC Register NANDECCn Field DescriptionsP8E P4E P2E P1E P8OAdditions/Modifications/Deletions Document Revision HistoryProducts Applications DSPRfid