Cypress CYV15G0404DXB manual Features, Functional Description

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CYV15G0404DXB

Independent Clock Quad HOTLink II™ Transceiver with Reclocker

Features

■Quad channel transceiver for 195 to 1500 MBaud serial signaling rate

❐Aggregate throughput of up to 12 Gbits/second

■Second-generation HOTLink® technology

■Compliant to multiple standards

❐SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ES- CON, and Gigabit Ethernet (IEEE802.3z)

❐10 bit uncoded data or 8B/10B coded data

■Truly independent channels

❐Each channel is able to:

•Perform reclocker function

•Operate at a different signaling rate

■Synchronous LVTTL parallel interface

■JTAG boundary scan

■Built In Self Test (BIST) for at-speed link testing

■Link quality indicator by channel

❐Analog signal detect

❐Digital signal detect

■Low power 3W at 3.3V typical

■Single 3.3V supply

■256 ball thermally enhanced BGA

■0.25μ BiCMOS technology

■JTAG device ID ‘0C811069’x

• Transport a different data format

■Internal phase-locked loops (PLLs) with no external PLL components

■Selectable differential PECL compatible serial inputs per channel

❐Internal DC restoration

■Redundant differential PECL compatible serial outputs per channel

❐No external bias resistors required

❐Signaling rate controlled edge rates

❐Source matched for 50Ω transmission lines

■MultiFrame™ Receive Framer provides alignment options

❐Comma or full K28.5 detect

❐Single or multibyte Framer for byte alignment

❐Low latency option

■Selectable input and output clocking options

Functional Description

The CYV15G0404DXB Independent Clock Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communica- tions building block enabling the transfer of data over a variety of high speed serial links including SMPTE 292, SMPTE 259, and DVB-ASI video applications. The signaling rate can be anywhere in the range of 195 to 1500 MBaud for each serial link. Each channel operates independently with its own reference clock allowing different rates. Each transmit channel accepts parallel characters in an input register, encodes each character for transport, and then converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. The received serial data can also be reclocked and retransmitted through the serial outputs. Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404DXB chips.

Figure 1. HOTLink II™ System Connections

 

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Video

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Independent

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Channel

 

Coprocessor

CYV15G0404DXB

 

Reclocker

 

 

 

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Serial Links

Serial Links

Serial Links

Serial Links

Cable

Connections

 

 

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Coprocessor

Independent

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Channel

 

 

CYV15G0404DXB

 

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Video

Reclocker

 

 

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Cypress Semiconductor Corporation • 198 Champion Court

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San Jose, CA 95134-1709

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408-943-2600

Document #: 38-02097 Rev. *B

 

Revised December 14, 2007

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramPhase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsStatus Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Device Control SignalsUse Local Clock . When Device Configuration and Control Bus Signals Link Fault Indication OutputControl Write Enable . Reframe Mode SelectCYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Modes Transmit BistTransmit PLL Clock Multiplier Serial Output Drivers Signal Detect/Link FaultCYV15G0404DXB Receive Data Path Serial Line ReceiversReclocker Clock/Data RecoveryDeserializer/Framer Receive Bist Operation 10B/8B Decoder BlockBits Detected FramerDevice Reset State Power ControlOutput Bus Receive Elasticity BufferOutput Register Bit Assignments Signal Name Device Configuration and Control InterfaceDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Name Signal Description Device Configuration and Control Latch DescriptionsRxckselb RxckselaRxckselc RxckseldTxrateb TxrateaTxratec TxratedDevice Control Latch Configuration Table Device Configuration StrategyRequired step Jtag SupportLevel Select Inputs Running disparity error . The character onNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBisterror Bistdatacompare 000 / BistcommandcompareBiststart RX PLLPower Up Requirements CYV15G0404DXB DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Power Supply TypCML Output Test Load Lvttl Output Test Load18Receiver Lvttl Switching Characteristics Over the Operating CYV15G0404DXB AC Electrical CharacteristicsREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitJtag Test Clock Characteristics Over the Operating Range Bus Configuration Write Timing Characteristics OverTransmit Serial Outputs and TX PLL Characteristics Over DeviceCapacitance20 CYV15G0404DXB HOTLink II Transmitter Switching WaveformsTransmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitWrite Timing REFCLKx selected Transmit InterfaceTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Reset Lvttl in PU VCC PowerCML Lvttl in PUTXDB6 Lvttl RXDC7 Lvttl OUTTXDC0 Lvttl RXDC4 Lvttl OUTNotation Conventions X3.230 Codes and Notation Conventions8B/10B Transmission Code Transmission OrderUse of the Tables for Generating Transmission Characters Code Violations Resulting from Prior ErrorsValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern Ordering Information Package DiagramCYV15G0404DXB-BGC CYV15G0404DXB-BGIAGT New Data SheetUKK/VED Methods to implement it
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