Cypress CYV15G0404DXB Link Fault Indication Output, Device Configuration and Control Bus Signals

Page 11

CYV15G0404DXB

Pin Definitions (continued)

CYV15G0404DXB Quad HOTLink II Transceiver

Name

I/O Characteristics

Signal Description

LFIA

LVTTL Output,

Link Fault Indication Output.

LFIx

is an output status indicator signal.

LFIx

is the

LFIB

asynchronous

logical OR of five internal conditions. LFIx is asserted LOW when any of these condi-

LFIC

 

tions are true:

LFID

 

■ Received serial data rate outside expected range

 

 

 

 

■ Analog amplitude below expected levels

 

 

■ Transition density lower than expected

 

 

■ Receive channel disabled

 

 

■

 

is LOW

 

 

ULCx

 

 

■ No REFCLKx±.

 

 

 

Device Configuration and Control Bus Signals

WREN

LVTTL input,

Control Write Enable. The

WREN

input writes the values of the DATA[7:0] bus into

 

asynchronous,

the latch specified by the address location on the ADDR[3:0] bus.[5]

 

internal pull up

 

 

 

 

 

 

 

 

 

 

 

ADDR[3:0]

LVTTL input

Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to

 

asynchronous,

configure the device. The WREN input writes the values of the DATA[7:0] bus into the

 

internal pull up

latch specified by the address location on the ADDR[3:0] bus.[5] Table 9 lists the

 

 

configuration latches within the device, and the initialization value of the latches upon

 

 

the assertion of RESET. Table 10 shows how the latches are mapped in the device.

DATA[7:0]

LVTTL input

Control Data Bus. The DATA[7:0] bus is the input data bus used to configure the

 

asynchronous,

device. The

WREN

input writes the values of the DATA[7:0] bus into the latch

 

internal pull up

specified by address location on the ADDR[3:0] bus.[5] Table 9 lists the configuration

 

 

latches within the device, and the initialization value of the latches upon the assertion

 

 

of RESET. Table 10 shows how the latches are mapped in the device.

Internal Device

Configuration Latches

 

 

 

 

 

 

 

 

 

 

 

RFMODE[A..D][1:0]

Internal Latch[6]

Reframe Mode Select.

FRAMCHAR[A..D]

Internal Latch[6]

Framing Character Select.

DECMODE[A..D]

Internal Latch[6]

Receiver Decoder Mode Select.

DECBYP[A..D]

Internal Latch[6]

Receiver Decoder Bypass.

RXCKSEL[A..D]

Internal Latch[6]

Receive Clock Select.

RXRATE[A..D]

Internal Latch[6]

Receive Clock Rate Select.

SDASEL[A..D][1:0]

Internal Latch[6]

Signal Detect Amplitude Select.

ENCBYP[A..D]

Internal Latch[6]

Transmit Encoder Bypass.

TXCKSEL[A..D]

Internal Latch[6]

Transmit Clock Select.

TXRATE[A..D]

Internal Latch[6]

Transmit PLL Clock Rate Select.

RFEN[A..D]

Internal Latch[6]

Reframe Enable.

RXPLLPD[A..D]

Internal Latch[6]

Receive Channel Power Control.

RXBIST[A..D]

Internal Latch[6]

Receive Bist Disabled.

TXBIST[A..D]

Internal Latch[6]

Transmit Bist Disabled.

OE2[A..D]

Internal Latch[6]

Differential Serial Output Driver 2 Enable.

OE1[A..D]

Internal Latch[6]

Differential Serial Output Driver 1 Enable.

PABRST[A..D]

Internal Latch[6]

Transmit Clock Phase Alignment Buffer Reset.

GLEN[11..0]

Internal Latch[6]

Global Latch Enable.

FGLEN[2..0]

Internal Latch[6]

Force Global Latch Enable.

Note

6. See Device Configuration and Control Interface for detailed information on the internal latches.

Document #: 38-02097 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramBist Lfsr Transmit Path Block DiagramPhase-Align rBuffe PLL Device Configura Tion and Control Interface Device Configuration and Control Block= Internal Signal Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsDevice Control Signals Name Characteristics Signal DescriptionStatus Signals Receive Path Clock SignalsUse Local Clock . When Reframe Mode Select Link Fault Indication OutputDevice Configuration and Control Bus Signals Control Write Enable .CYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit PLL Clock Multiplier Transmit BistTransmit Modes Serial Line Receivers Signal Detect/Link FaultSerial Output Drivers CYV15G0404DXB Receive Data PathDeserializer/Framer Clock/Data RecoveryReclocker Framer 10B/8B Decoder BlockReceive Bist Operation Bits DetectedReceive Elasticity Buffer Power ControlDevice Reset State Output BusDECBYPx = Decbyp = Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name Decoder Bypass Mode Signal Name Bus Weight Bit NameName Signal Description Device Configuration and Control Latch DescriptionsRxckseld RxckselaRxckselb RxckselcTxrated TxrateaTxrateb TxratecJtag Support Device Configuration StrategyDevice Control Latch Configuration Table Required stepReceive Elasticity buffer underrun/overrun Running disparity error . The character onLevel Select Inputs Normal character received . The valid DataRX PLL Bistdatacompare 000 / BistcommandcompareBisterror BiststartOperating Range CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Maximum RatingsLvttl Output Test Load18 Power Supply TypAC Test Loads and Waveforms CML Output Test LoadParameter Description Min Max Unit CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating REFCLKx Switching Characteristics Over the Operating RangeDevice Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range Transmit Serial Outputs and TX PLL Characteristics OverParameter Description Test Conditions Max Unit CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Transmit Interface Write Timing REFCLKx selected TXRATEx =TXCTx10 Transmit InterfaceWrite Timing REFCLKx selected TXDx70REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Lvttl in PU VCC PowerReset Lvttl in PU CMLRXDC4 Lvttl OUT RXDC7 Lvttl OUTTXDB6 Lvttl TXDC0 LvttlTransmission Order X3.230 Codes and Notation ConventionsNotation Conventions 8B/10B Transmission CodeHex Value Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Valid Transmission Characters Data Byte NameAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Violation Pattern End of Frame SequenceCode Rule Violation and SVS Tx Pattern CYV15G0404DXB-BGI Package DiagramOrdering Information CYV15G0404DXB-BGCMethods to implement it New Data SheetAGT UKK/VED
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