Cypress manual Maximum Ratings, CYV15G0404DXB DC Electrical Characteristics, Operating Range

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CYV15G0404DXB

Maximum Ratings

Exceeding maximum ratings may impair the useful life of device. These user guidelines are not tested.

Static Discharge Voltage

> 2000 V

(according to MIL-STD-883, Method 3015)

 

Latch-up Current

> 200 mA

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

 

Power Applied

–55°C to +125°C

Supply Voltage to Ground Potential

–0.5V to +3.8V

DC Voltage Applied to LVTTL Outputs

 

 

in High-Z State

–0.5V to VCC + 0.5V

Output Current into LVTTL Outputs (LOW)

................. 60 mA

DC Input Voltage

–0.5V to VCC + 0.5V

CYV15G0404DXB DC Electrical Characteristics

Power Up Requirements

The CYP(V)15G0404DXB requires one power supply. The Voltage on any input or IO pin cannot exceed the power pin during power up.

Operating Range

Range

Ambient Temperature

VCC

Commercial

0°C to +70°C

+3.3V ±5%

Industrial

–40°C to +85°C

+3.3V ±5%

Parameter

Description

Test Conditions

Min.

Max.

Unit

LVTTL-compatible Outputs

 

 

 

 

 

 

 

 

 

 

VOHT

Output HIGH Voltage

IOH = 4 mA, VCC = Min.

2.4

 

V

VOLT

Output LOW Voltage

IOL = 4 mA, VCC = Min.

 

0.4

V

IOST

Output Short Circuit Current

VOUT = 0V[12], VCC = 3.3V

–20

–100

mA

IOZL

High-Z Output Leakage Current

VOUT = 0V, VCC

–20

20

µA

LVTTL-compatible Inputs

 

 

 

 

VIHT

Input HIGH Voltage

 

2.0

VCC + 0.3

V

VILT

Input LOW Voltage

 

–0.5

0.8

V

IIHT

Input HIGH Current

REFCLKx Input, VIN = VCC

 

1.5

mA

 

 

Other Inputs, VIN = VCC

 

+40

µA

IILT

Input LOW Current

REFCLKx Input, VIN = 0.0V

 

–1.5

mA

 

 

Other Inputs, VIN = 0.0V

 

–40

µA

IIHPDT

Input HIGH Current with internal pull down

VIN = VCC

 

+200

µA

IILPUT

Input LOW Current with internal pull up

VIN = 0.0V

 

–200

µA

LVDIFF Inputs: REFCLKx±

 

 

 

 

VDIFF[13]

Input Differential Voltage

 

400

VCC

mV

VIHHP

Highest Input HIGH Voltage

 

1.2

VCC

V

VILLP

Lowest Input LOW voltage

 

0.0

VCC/2

V

VCOMREF[14]

Common Mode Range

 

1.0

VCC – 1.2V

V

3-Level Inputs

 

 

 

 

 

 

 

 

 

 

VIHH

Three-Level Input HIGH Voltage

Min. VCC Max.

0.87 * VCC

VCC

V

VIMM

Three-Level Input MID Voltage

Min. VCC Max.

0.47 * VCC

0.53 * VCC

V

VILL

Three-Level Input LOW Voltage

Min. VCC Max.

0.0

0.13 * VCC

V

IIHH

Input HIGH Current

VIN = VCC

 

200

µA

IIMM

Input MID current

VIN = VCC/2

–50

50

µA

IILL

Input LOW current

VIN = GND

 

–200

µA

Notes

12.Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

13.This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the true (+) input is more positive than the complement (-) input. A logic-0 exists when the complement (-) input is more positive than true (+) input.

14.The common mode range defines the allowable range of REFCLKx+ and REFCLKx- when REFCLKx+ = REFCLKx-. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.

Document #: 38-02097 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerBist Lfsr Transmit Path Block DiagramPhase-Align rBuffe PLL Device Configura Tion and Control Interface Device Configuration and Control Block= Internal Signal Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverReceive Path Clock Signals Name Characteristics Signal DescriptionStatus Signals Device Control SignalsUse Local Clock . When Control Write Enable . Link Fault Indication OutputDevice Configuration and Control Bus Signals Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit PLL Clock Multiplier Transmit BistTransmit Modes CYV15G0404DXB Receive Data Path Signal Detect/Link FaultSerial Output Drivers Serial Line ReceiversDeserializer/Framer Clock/Data RecoveryReclocker Bits Detected 10B/8B Decoder BlockReceive Bist Operation FramerOutput Bus Power ControlDevice Reset State Receive Elasticity BufferDecoder Bypass Mode Signal Name Bus Weight Bit Name Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxckselc RxckselaRxckselb RxckseldTxratec TxrateaTxrateb TxratedRequired step Device Configuration StrategyDevice Control Latch Configuration Table Jtag SupportNormal character received . The valid Data Running disparity error . The character onLevel Select Inputs Receive Elasticity buffer underrun/overrunBiststart Bistdatacompare 000 / BistcommandcompareBisterror RX PLLMaximum Ratings CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Operating RangeCML Output Test Load Power Supply TypAC Test Loads and Waveforms Lvttl Output Test Load18REFCLKx Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating Parameter Description Min Max UnitTransmit Serial Outputs and TX PLL Characteristics Over Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range DeviceTransmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Parameter Description Test Conditions Max UnitTXDx70 Transmit InterfaceWrite Timing REFCLKx selected TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing CML VCC PowerReset Lvttl in PU Lvttl in PUTXDC0 Lvttl RXDC7 Lvttl OUTTXDB6 Lvttl RXDC4 Lvttl OUT8B/10B Transmission Code X3.230 Codes and Notation ConventionsNotation Conventions Transmission OrderValid Transmission Characters Data Byte Name Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Violation Pattern End of Frame SequenceCode Rule Violation and SVS Tx Pattern CYV15G0404DXB-BGC Package DiagramOrdering Information CYV15G0404DXB-BGIUKK/VED New Data SheetAGT Methods to implement it