Cypress CYV15G0404DXB manual Level Select Inputs, Normal character received . The valid Data

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CYV15G0404DXB

3-Level Select Inputs

Each 3-Level select inputs reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11 respectively.

JTAG ID

The JTAG device ID for the CYV15G0404DXB is ‘0C811069’x

.

Receive Character Status Bits

RXSTx[2:0]	Priority	Description
RXSTx[2:0]	Priority	Normal Status	Receive BIST Status
		Normal Status	(Receive BIST = Enabled)
			(Receive BIST = Enabled)
000	7	Normal character received. The valid Data	BIST Data Compare. Character compared correctly.
		character on the output bus meets all the
		formatting requirements of Data characters
		listed in Table 14.
001	7	Special code detected. The valid special	BIST Command Compare. Character compared
		character on the output bus meets all the	correctly.
		formatting requirements of Special Code
		characters listed in Table 15, but is not the
		presently selected framing character or a
		decoder violation indication.
010	2	Receive Elasticity buffer underrun/overrun	BIST Last Good. Last Character of BIST sequence
		error. The receive buffer was not able to	detected and valid.
		add/drop a K28.5 or framing character
011	5	Framing character detected. This indicates
		that a character matching the patterns identified
		as a framing character (as selected by
		FRAMCHARx) was detected. The decoded
		value of this character is present in the
		associated output bus.
100	4	Codeword violation. The character on the	BIST Last Bad. Last Character of BIST sequence
		output bus is a C0.7. This indicates that the	detected invalid.
		received character cannot be decoded into any
		valid character.
101	1	Loss of sync. This indicates a PLL Out of Lock	BIST Start. Receive BIST is enabled on this channel,
		condition	but character compares have not yet commenced. This
			also indicates a PLL Out of Lock condition, and
			Elasticity Buffer overflow/underflow conditions.
110	6	Running disparity error. The character on the	BIST Error. While comparing characters, a mismatch
		output bus is a C4.7, C1.7, or C2.7.	was found in one or more of the decoded character bits.
111	3	Reserved	BIST Wait. The receiver is comparing characters. but
			has not yet found the start of BIST character to enable
			the LFSR.

Document #: 38-02097 Rev. *B

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Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerTransmit Path Block Diagram Phase-Align rBuffeBist Lfsr PLL Device Configuration and Control Block = Internal SignalDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverName Characteristics Signal Description Status SignalsReceive Path Clock Signals Device Control SignalsUse Local Clock . When Link Fault Indication Output Device Configuration and Control Bus SignalsControl Write Enable . Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit Bist Transmit ModesTransmit PLL Clock Multiplier Signal Detect/Link Fault Serial Output DriversCYV15G0404DXB Receive Data Path Serial Line ReceiversClock/Data Recovery ReclockerDeserializer/Framer 10B/8B Decoder Block Receive Bist OperationBits Detected FramerPower Control Device Reset StateOutput Bus Receive Elasticity BufferDevice Configuration and Control Interface Output Register Bit Assignments Signal NameDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxcksela RxckselbRxckselc RxckseldTxratea TxratebTxratec TxratedDevice Configuration Strategy Device Control Latch Configuration TableRequired step Jtag SupportRunning disparity error . The character on Level Select InputsNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBistdatacompare 000 / Bistcommandcompare BisterrorBiststart RX PLLCYV15G0404DXB DC Electrical Characteristics Power Up RequirementsMaximum Ratings Operating RangePower Supply Typ AC Test Loads and WaveformsCML Output Test Load Lvttl Output Test Load18CYV15G0404DXB AC Electrical Characteristics Receiver Lvttl Switching Characteristics Over the OperatingREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitBus Configuration Write Timing Characteristics Over Jtag Test Clock Characteristics Over the Operating RangeTransmit Serial Outputs and TX PLL Characteristics Over DeviceCYV15G0404DXB HOTLink II Transmitter Switching Waveforms Capacitance20Transmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitTransmit Interface Write Timing REFCLKx selectedTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing VCC Power Reset Lvttl in PUCML Lvttl in PURXDC7 Lvttl OUT TXDB6 LvttlTXDC0 Lvttl RXDC4 Lvttl OUTX3.230 Codes and Notation Conventions Notation Conventions8B/10B Transmission Code Transmission OrderCode Violations Resulting from Prior Errors Use of the Tables for Generating Transmission CharactersValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB End of Frame Sequence Code Rule Violation and SVS Tx PatternViolation Pattern Package Diagram Ordering InformationCYV15G0404DXB-BGC CYV15G0404DXB-BGINew Data Sheet AGTUKK/VED Methods to implement it