Cypress CYV15G0404DXB manual Device Configuration and Control Interface, DECBYPx = Decbyp =

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CYV15G0404DXB

Table 7. Output Register Bit Assignments

Signal Name

BYPASS ACTIVE

DECODER

(DECBYPx = 0)

(DECBYP = 1)

 

RXSTx[2] (LSB)

COMDETx

RXSTx[2]

 

 

 

RXSTx[1]

DOUTx[0]

RXSTx[1]

 

 

 

RXSTx[0]

DOUTx[1]

RXSTx[0]

 

 

 

RXDx[0]

DOUTx[2]

RXDx[0]

 

 

 

RXDx[1]

DOUTx[3]

RXDx[1]

 

 

 

RXDx[2]

DOUTx[4]

RXDx[2]

 

 

 

RXDx[3]

DOUTx[5]

RXDx[3]

 

 

 

RXDx[4]

DOUTx[6]

RXDx[4]

 

 

 

RXDx[5]

DOUTx[7]

RXDx[5]

 

 

 

RXDx[6]

DOUTx[8]

RXDx[6]

 

 

 

RXDx[7] (MSB)

DOUTx[9]

RXDx[7]

 

 

 

When the 10B/8B decoder is bypassed, the framed 10-bit value is presented to the associated output register, along with a status output signal indicating if the character in the output register is one of the selected framing characters. The bit usage and mapping of the external signals to the raw 10B transmission character is shown in Table 8.

Table 8. Decoder Bypass Mode

Signal Name

Bus Weight

10 Bit Name

RXSTx[2] (LSB)

COMDETx

 

 

 

 

RXSTx[1]

20

a

RXSTx[0]

21

b

RXDx[0]

22

c

RXDx[1]

23

d

RXDx[2]

24

e

RXDx[3]

25

i

RXDx[4]

26

f

RXDx[5]

27

g

RXDx[6]

28

h

RXDx[7] (MSB)

29

j

The COMDETx status output operates the same regardless of the bit combination selected for character framing by the FRAMCHARx latch. COMDETx is HIGH when the character in the output register contains the selected framing character at the proper character boundary, and LOW for all other bit combina- tions.

When the low-latency framer and half rate receive port clocking are also enabled, the framer stretches the recovered clock to the nearest 20-bit boundary such that the rising edge of RXCLKx+ occurs when COMDETx is present on the associated output bus.

When the Cypress or alternate mode framer is enabled and half rate receive port clocking is also enabled, the output clock is not modified when framing is detected, but a single pipeline stage may be added or subtracted from the data stream by the framer logic such that the rising edge of RXCLKx+ occurs when COMDETx is present on the associated output bus.

This adjustment only occurs when the framer is enabled. When the framer is disabled, the clock boundaries are not adjusted, and COMDETx may be asserted during the rising edge of RXCLKx– (if an odd number of characters were received following the initial framing).

Receive Status Bits

When the 10B/8B decoder is enabled, each character presented at the output register includes three associated status bits. These bits are used to identify

If the contents of the data bus are valid

The type of character present

The state of receive BIST operations

Character violations

These conditions often overlap; for example, a valid data character received with incorrect running disparity is not reported as a valid data character. It is instead reported as a decoder violation of some specific type. This implies a hierarchy or priority level to the various status bit combinations. The hierarchy and value of each status are listed in Table 11.

A second status mapping, listed in Table 11, is used when the receive channel is configured for BIST operation. This status is used to report receive BIST status and progress.

BIST Status State Machine

When a receive path is enabled to look for and compare the received data stream with the BIST pattern, the RXSTx[2:0] bits identify the present state of the BIST compare operation.

The BIST state machine has multiple states, as shown in Figure 2 and Table 11. When the receive PLL detects an out-of-lock condition, the BIST state is forced to the Start-of-BIST state, regardless of the present state of the BIST state machine. If the number of detected errors ever exceeds the number of valid matches by greater than 16, the state machine is forced to the WAIT_FOR_BIST state where it monitors the receive path for the first character of the next BIST sequence (D0.0). Also, if the Elasticity Buffer ever hits an overflow/underflow condition, the status is forced to the BIST_START until the buffer is re-centered (approximately nine character periods).

To ensure compatibility between the source and destination systems when operating in BIST modes, the sending and receiving ends of the link must use the same receive clock configuration.

Device Configuration and Control Interface

The CYP(V)15G0404DX is highly configurable through the configuration interface. The configuration interface allows the device to be configured globally or allows each channel to be configured independently. Table 9 lists the configuration latches within the device including the initialization value of the latches upon the assertion of RESET. Table 10 shows how the latches are mapped in the device. Each row in the Table 10 maps to a 8-bit latch bank. There are 16 such write-only latch banks. When WREN = 0, the logic value in the DATA[7:0] is latched to the latch bank specified by the values in ADDR[3:0]. The second column of Table 10 specifies the channels associated with the corre- sponding latch bank. For example, the first three latch banks (0,1 and 2) consist of configuration bits for channel A. The latch banks

Document #: 38-02097 Rev. *B

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramPhase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsDevice Control Signals Name Characteristics Signal DescriptionStatus Signals Receive Path Clock SignalsUse Local Clock . When Reframe Mode Select Link Fault Indication OutputDevice Configuration and Control Bus Signals Control Write Enable .CYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Modes Transmit BistTransmit PLL Clock Multiplier Serial Line Receivers Signal Detect/Link FaultSerial Output Drivers CYV15G0404DXB Receive Data PathReclocker Clock/Data RecoveryDeserializer/Framer Framer 10B/8B Decoder BlockReceive Bist Operation Bits DetectedReceive Elasticity Buffer Power ControlDevice Reset State Output BusDECBYPx = Decbyp = Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name Decoder Bypass Mode Signal Name Bus Weight Bit NameName Signal Description Device Configuration and Control Latch DescriptionsRxckseld RxckselaRxckselb RxckselcTxrated TxrateaTxrateb TxratecJtag Support Device Configuration StrategyDevice Control Latch Configuration Table Required stepReceive Elasticity buffer underrun/overrun Running disparity error . The character onLevel Select Inputs Normal character received . The valid DataRX PLL Bistdatacompare 000 / BistcommandcompareBisterror BiststartOperating Range CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Maximum RatingsLvttl Output Test Load18 Power Supply TypAC Test Loads and Waveforms CML Output Test LoadParameter Description Min Max Unit CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating REFCLKx Switching Characteristics Over the Operating RangeDevice Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range Transmit Serial Outputs and TX PLL Characteristics OverParameter Description Test Conditions Max Unit CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Transmit Interface Write Timing REFCLKx selected TXRATEx =TXCTx10 Transmit InterfaceWrite Timing REFCLKx selected TXDx70REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Lvttl in PU VCC PowerReset Lvttl in PU CMLRXDC4 Lvttl OUT RXDC7 Lvttl OUTTXDB6 Lvttl TXDC0 LvttlTransmission Order X3.230 Codes and Notation ConventionsNotation Conventions 8B/10B Transmission CodeHex Value Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Valid Transmission Characters Data Byte NameAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern CYV15G0404DXB-BGI Package DiagramOrdering Information CYV15G0404DXB-BGCMethods to implement it New Data SheetAGT UKK/VED