CYV15G0404DXB
Table 7. Output Register Bit Assignments
Signal Name | BYPASS ACTIVE | DECODER | |
(DECBYPx = 0) | (DECBYP = 1) | ||
| |||
RXSTx[2] (LSB) | COMDETx | RXSTx[2] | |
|
|
| |
RXSTx[1] | DOUTx[0] | RXSTx[1] | |
|
|
| |
RXSTx[0] | DOUTx[1] | RXSTx[0] | |
|
|
| |
RXDx[0] | DOUTx[2] | RXDx[0] | |
|
|
| |
RXDx[1] | DOUTx[3] | RXDx[1] | |
|
|
| |
RXDx[2] | DOUTx[4] | RXDx[2] | |
|
|
| |
RXDx[3] | DOUTx[5] | RXDx[3] | |
|
|
| |
RXDx[4] | DOUTx[6] | RXDx[4] | |
|
|
| |
RXDx[5] | DOUTx[7] | RXDx[5] | |
|
|
| |
RXDx[6] | DOUTx[8] | RXDx[6] | |
|
|
| |
RXDx[7] (MSB) | DOUTx[9] | RXDx[7] | |
|
|
|
When the 10B/8B decoder is bypassed, the framed
Table 8. Decoder Bypass Mode
Signal Name | Bus Weight | 10 Bit Name |
RXSTx[2] (LSB) | COMDETx |
|
|
|
|
RXSTx[1] | 20 | a |
RXSTx[0] | 21 | b |
RXDx[0] | 22 | c |
RXDx[1] | 23 | d |
RXDx[2] | 24 | e |
RXDx[3] | 25 | i |
RXDx[4] | 26 | f |
RXDx[5] | 27 | g |
RXDx[6] | 28 | h |
RXDx[7] (MSB) | 29 | j |
The COMDETx status output operates the same regardless of the bit combination selected for character framing by the FRAMCHARx latch. COMDETx is HIGH when the character in the output register contains the selected framing character at the proper character boundary, and LOW for all other bit combina- tions.
When the
When the Cypress or alternate mode framer is enabled and half rate receive port clocking is also enabled, the output clock is not modified when framing is detected, but a single pipeline stage may be added or subtracted from the data stream by the framer logic such that the rising edge of RXCLKx+ occurs when COMDETx is present on the associated output bus.
This adjustment only occurs when the framer is enabled. When the framer is disabled, the clock boundaries are not adjusted, and COMDETx may be asserted during the rising edge of RXCLKx– (if an odd number of characters were received following the initial framing).
Receive Status Bits
When the 10B/8B decoder is enabled, each character presented at the output register includes three associated status bits. These bits are used to identify
■If the contents of the data bus are valid
■The type of character present
■The state of receive BIST operations
■Character violations
These conditions often overlap; for example, a valid data character received with incorrect running disparity is not reported as a valid data character. It is instead reported as a decoder violation of some specific type. This implies a hierarchy or priority level to the various status bit combinations. The hierarchy and value of each status are listed in Table 11.
A second status mapping, listed in Table 11, is used when the receive channel is configured for BIST operation. This status is used to report receive BIST status and progress.
BIST Status State Machine
When a receive path is enabled to look for and compare the received data stream with the BIST pattern, the RXSTx[2:0] bits identify the present state of the BIST compare operation.
The BIST state machine has multiple states, as shown in Figure 2 and Table 11. When the receive PLL detects an
To ensure compatibility between the source and destination systems when operating in BIST modes, the sending and receiving ends of the link must use the same receive clock configuration.
Device Configuration and Control Interface
The CYP(V)15G0404DX is highly configurable through the configuration interface. The configuration interface allows the device to be configured globally or allows each channel to be configured independently. Table 9 lists the configuration latches within the device including the initialization value of the latches upon the assertion of RESET. Table 10 shows how the latches are mapped in the device. Each row in the Table 10 maps to a
Document #: | Page 19 of 44 |
[+] Feedback