Cypress CYV15G0404DXB manual Pin Configuration Top View

Page 6

CYV15G0404DXB

Pin Configuration (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

IN

OUT

IN

OUT

VCC

IN

OUT

GND

IN

OUT

IN

OUT

GND

IN

OUT

VCC

IN

OUT

IN

OUT

C1–

C1–

C2–

C2–

D1–

D1–

D2–

D2–

A1–

A1–

A2–

A2–

B1–

B1–

B2–

B2–

B

IN

OUT

IN

OUT

VCC

IN

OUT

GND

IN

OUT

IN

OUT

GND

IN

OUT

VCC

IN

OUT

IN

OUT

C1+

C1+

C2+

C2+

D1+

D1+

D2+

D2+

A1+

A1+

A2+

A2+

B1+

B1+

B2+

B2+

C

TDI

TMS

INSELC

INSELB

V

CC

ULCD

ULCC

GND

DATA

DATA

DATA

DATA

GND

RCLK

SPD

V

LDTD

TRST

LPEND

TDO

[7]

[5]

[3]

[1]

ENB

SELD

CC

EN

D

TCLK

INSELD

INSELA

V

CC

ULCA

SPD

GND

DATA

DATA

DATA

DATA

GND

LPENB

ULCB

V

LPENA

VCC

SCAN

TMEN3

SELC

[6]

[4]

[2]

[0]

CC

EN2

E

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

F

RX

RX

TX

RCLK

RCLK

RX

TX

RX

DC[6]

DC[7]

DC[0]

END

ENA

STB[1]

CLKOB

STB[0]

G

TX

WREN

TX

TX

SPD

LP

SPD

RX

DC[7]

DC[4]

DC[1]

SELB

ENC

SELA

DB[1]

H

GND

GND

GND

GND

GND

GND

GND

GND

J

TX

TX

TX

TX

RX

RX

RX

RX

CTC[1]

DC[5]

DC[2]

DC[3]

STB[2]

DB[0]

DB[5]

DB[2]

K

RX

REF

TX

TX

RX

RX

RX

LFIB

DC[2]

CLKC–

CTC[0]

CLKC

DB[3]

DB[4]

DB[7]

L

RX

REF

LFIC

TX

RX

RX

RX

TX

DC[3]

CLKC+

DC[6]

DB[6]

CLKB+

CLKB–

DB[6]

M

RX

RX

RCLK

TX

REF

REF

TX

TX

DC[4]

DC[5]

ENC

ERRC

CLKB+

CLKB–

ERRB

CLKB

N

GND

GND

GND

GND

GND

GND

GND

GND

P

RX

RX

RX

RX

TX

TX

TX

TX

DC[1]

DC[0]

STC[0]

STC[1]

DB[5]

DB[4]

DB[3]

DB[2]

R

RX

TX

RX

RX

TX

TX

TX

TX

STC[2]

CLKOC

CLKC+

CLKC–

DB[1]

DB[0]

CTB[1]

DB[7]

T

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U

TX

TX

TX

TX

VCC

RX

RX

GND

TX

ADDR

REF

TX

GND

TX

TX

VCC

RX

TX

RX

RX

DD[0]

DD[1]

DD[2]

CTD[1]

DD[2]

DD[1]

CTA[1]

[0]

CLKD–

DA[1]

DA[4]

CTA[0]

DA[2]

CTB[0]

STA[2]

STA[1]

V

TX

TX

TX

RX

VCC

RX

RX

GND

RX

ADDR

REF

TX

GND

TX

TX

VCC

RX

RX

RX

RX

DD[3]

DD[4]

CTD[0]

DD[6]

DD[3]

STD[0]

STD[2]

[2]

CLKD+

CLKOA

DA[3]

DA[7]

DA[7]

DA[3]

DA[0]

STA[0]

W

TX

TX

LFID

RX

VCC

RX

RX

GND

ADDR

ADDR

RX

TX

GND

TX

TX

VCC

LFIA

REF

RX

RX

DD[5]

DD[7]

CLKD–

DD[4]

STD[1]

[3]

[1]

CLKA+

ERRA

DA[2]

DA[6]

CLKA+

DA[4]

DA[1]

Y

TX

TX

RX

RX

VCC

RX

RX

GND

TX

NC[1]

TX

RX

GND

TX

TX

VCC

TX

REF

RX

RX

DD[6]

CLKD

DD[7]

CLKD+

DD[5]

DD[0]

CLKOD

CLKA

CLKA–

DA[0]

DA[5]

ERRD

CLKA–

DA[6]

DA[5]

Document #: 38-02097 Rev. *B

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Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerTransmit Path Block Diagram Phase-Align rBuffeBist Lfsr PLL Device Configuration and Control Block = Internal SignalDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverReceive Path Clock Signals Name Characteristics Signal DescriptionStatus Signals Device Control SignalsUse Local Clock . When Control Write Enable . Link Fault Indication OutputDevice Configuration and Control Bus Signals Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit Bist Transmit ModesTransmit PLL Clock Multiplier CYV15G0404DXB Receive Data Path Signal Detect/Link FaultSerial Output Drivers Serial Line ReceiversClock/Data Recovery ReclockerDeserializer/Framer Bits Detected 10B/8B Decoder BlockReceive Bist Operation FramerOutput Bus Power ControlDevice Reset State Receive Elasticity BufferDecoder Bypass Mode Signal Name Bus Weight Bit Name Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxckselc RxckselaRxckselb RxckseldTxratec TxrateaTxrateb TxratedRequired step Device Configuration StrategyDevice Control Latch Configuration Table Jtag SupportNormal character received . The valid Data Running disparity error . The character onLevel Select Inputs Receive Elasticity buffer underrun/overrunBiststart Bistdatacompare 000 / BistcommandcompareBisterror RX PLLMaximum Ratings CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Operating RangeCML Output Test Load Power Supply TypAC Test Loads and Waveforms Lvttl Output Test Load18REFCLKx Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating Parameter Description Min Max UnitTransmit Serial Outputs and TX PLL Characteristics Over Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range DeviceTransmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Parameter Description Test Conditions Max UnitTXDx70 Transmit InterfaceWrite Timing REFCLKx selected TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing CML VCC PowerReset Lvttl in PU Lvttl in PUTXDC0 Lvttl RXDC7 Lvttl OUTTXDB6 Lvttl RXDC4 Lvttl OUT8B/10B Transmission Code X3.230 Codes and Notation ConventionsNotation Conventions Transmission OrderValid Transmission Characters Data Byte Name Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB End of Frame Sequence Code Rule Violation and SVS Tx PatternViolation Pattern CYV15G0404DXB-BGC Package DiagramOrdering Information CYV15G0404DXB-BGIUKK/VED New Data SheetAGT Methods to implement it