Cypress CYV15G0404DXB Txratea, Txrateb, Txratec, Txrated, Rfena, Rfenb, Rfenc, Rfend, Rxpllpda

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CYV15G0404DXB

 

 

 

 

 

 

 

 

 

 

Table 9. Device Configuration and Control Latch Descriptions (continued)

 

 

 

Name

Signal Description

 

 

TXRATEA

Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to select

 

 

TXRATEB

the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the associated

 

TXRATEC

REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx output clocks

 

TXRATED

are full rate clocks and follow the frequency and duty cycle of the associated REFCLKx± input. When

 

 

TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by 20 to generate the serial

 

 

bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the REFCLKx±

 

 

input. When TXCKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using both the rising

 

 

and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx is LOW, is an invalid state and this combination

 

 

is reserved.

 

RFENA

Reframe Enable. The initialization value of the RFENx latch = 1. RFENx selects if the receiver framer is

 

 

RFENB

enabled or disabled. When RFENx = 1, the associated channel’s framer is enabled to frame per the presently

 

RFENC

enabled framing mode and selected framing character. When RFENx = 0, the associated channel’s framer is

 

RFEND

disabled, and no received bits alters the frame offset.

 

RXPLLPDA

Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the

 

 

RXPLLPDB

associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated PLL and

 

RXPLLPDC

analog circuitry is powered-down. When RXPLLPDx = 1, the associated PLL and analog circuitry is enabled.

 

RXPLLPDD

 

 

 

 

 

RXBISTA

Receive Bist Disabled. The initialization value of the RXBISTx latch = 1. RXBISTx selects if receive BIST is

 

 

RXBISTB

disabled or enabled. When RXBISTx = 1, the receiver BIST function is disabled. When RXBISTx = 0, the

 

RXBISTC

receive BIST function is enabled.

 

RXBISTD

 

 

 

 

 

TXBISTA

Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit BIST

 

 

TXBISTB

is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0, the

 

TXBISTC

transmit BIST function is enabled.

 

TXBISTD

 

 

 

 

 

OE2A

Secondary Differential Serial Data Output Driver Enable. The initialization value of the OE2x latch = 0.

 

 

OE2B

OE2x selects if the OUT2± secondary differential output drivers are enabled or disabled. When OE2x = 1, the

 

OE2C

associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When

 

OE2D

OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration

 

 

interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this

 

 

disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET

 

 

sampled LOW) disables all output drivers.

 

OE1A

Primary Differential Serial Data Output Driver Enable. The initialization value of the OE1x latch = 0. OE1x

 

 

OE1B

selects if the OUT1± primary differential output drivers are enabled or disabled. When OE1x = 1, the associated

 

OE1C

serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When OE1x = 0,

 

OE1D

the associated serial data output driver is disabled. When a driver is disabled via the configuration interface,

 

 

it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled

 

 

state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled

 

 

LOW) disables all output drivers.

 

PABRSTA

Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The

 

 

PABRSTB

PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is

 

PABRSTC

written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized. PABRST

 

PABRSTD

is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal clock domain.

 

 

PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the initialization of

 

 

the Phase Alignment Buffer.

 

GLEN[11..0]

Global Enable. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several

 

 

 

channels simultaneously in applications where several channels may have the same configuration. When

 

 

GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When GLENx

 

 

= 0 for a given address, that address is disabled from participating in a global configuration.

 

FGLEN[2..0]

Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a GLobal

 

 

 

ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global channel,

 

 

FGLEN forces the global update of the target latch banks.

 

Document #: 38-02097 Rev. *B

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Contents Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerPhase-Align rBuffe Transmit Path Block DiagramBist Lfsr PLL = Internal Signal Device Configuration and Control BlockDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverReceive Path Clock Signals Name Characteristics Signal DescriptionStatus Signals Device Control SignalsUse Local Clock . When Control Write Enable . Link Fault Indication OutputDevice Configuration and Control Bus Signals Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit Modes Transmit BistTransmit PLL Clock Multiplier CYV15G0404DXB Receive Data Path Signal Detect/Link FaultSerial Output Drivers Serial Line ReceiversReclocker Clock/Data RecoveryDeserializer/Framer Bits Detected 10B/8B Decoder BlockReceive Bist Operation FramerOutput Bus Power ControlDevice Reset State Receive Elasticity BufferDecoder Bypass Mode Signal Name Bus Weight Bit Name Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxckselc RxckselaRxckselb RxckseldTxratec TxrateaTxrateb TxratedRequired step Device Configuration StrategyDevice Control Latch Configuration Table Jtag SupportNormal character received . The valid Data Running disparity error . The character onLevel Select Inputs Receive Elasticity buffer underrun/overrunBiststart Bistdatacompare 000 / BistcommandcompareBisterror RX PLLMaximum Ratings CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Operating RangeCML Output Test Load Power Supply TypAC Test Loads and Waveforms Lvttl Output Test Load18REFCLKx Switching Characteristics Over the Operating Range CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating Parameter Description Min Max UnitTransmit Serial Outputs and TX PLL Characteristics Over Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range DeviceTransmit Interface Write Timing REFCLKx selected TXRATEx = CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Parameter Description Test Conditions Max UnitTXDx70 Transmit InterfaceWrite Timing REFCLKx selected TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing CML VCC PowerReset Lvttl in PU Lvttl in PUTXDC0 Lvttl RXDC7 Lvttl OUTTXDB6 Lvttl RXDC4 Lvttl OUT8B/10B Transmission Code X3.230 Codes and Notation ConventionsNotation Conventions Transmission OrderValid Transmission Characters Data Byte Name Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Code Rule Violation and SVS Tx Pattern End of Frame SequenceViolation Pattern CYV15G0404DXB-BGC Package DiagramOrdering Information CYV15G0404DXB-BGIUKK/VED New Data SheetAGT Methods to implement it
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