Cypress CYV15G0404DXB manual Transmit Path Block Diagram, Phase-Align rBuffe, Bist Lfsr

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CYV15G0404DXB

Transmit Path Block Diagram

RECLCK[A..D] are Internal Reclocker Signals

REFCLKA+

Bit-Rate Clock

TXLB[A..D] are Internal Serial Loopback Signals

REFCLKA–

= Internal Signal

TXRATEA

TransmitPLL

OEA[2..1]

ClockMultiplierA

SPDSELA

ENCBYPA

TXCLKOA

Character-Rate Clock A

RECLCKA

TXERRA

TXBISTA

OEA[2..1]

TXCLKA

PABRSTA

0

1

TXCKSELA

Phase-Align rBuffe

TXDA[7:0]

8

10

10

10

OUTA1+

10

OUTA1–

TXCTA[1:0]

2

Input Register

Encoder8B/10B

Encoder

BISTLFSR

Shifter

OUTA2+

OUTA2–

REFCLKB+

TXLBA

Bit-Rate Clock

REFCLKB–

Transmit PLL

TXRATEB

OEB[2..1]

Clock Multiplier B

SPDSELB

ENCBYPB

TXCLKOB

Character-Rate Clock B

RECLCKB

TXERRB

PABRSTB

TXBISTB

TXCLKB

OEB[2..1]

0

TXCKSELB

1

Phase-Align rBuffe

8

Register

10

10

8B/10B Encoder

10

BIST LFSR

10

Shifter

OUTB1+

Input

OUTB1–

TXDB[7:0]

OUTB2+

2

TXCTB[1:0]

OUTB2–

TXLBB

REFCLKC+

Bit-Rate Clock

REFCLKC–

Transmit PLL

TXRATEC

OEC[2..1]

Clock Multiplier C

SPDSELC

ENCBYPC

RECLCKC

TXCLKOC

Character-Rate Clock C

TXERRC

OEC[2..1]

PABRSTC

TXBISTC

TXCLKC

TXCKSELC

0

1

TXDC[7:0]

8

Input Register

Phase-Align

8B/10B

Encoder

BIST LFSR

OUTC1+

10

Buffer

10

10

10

Shifter

2

OUTC1–

TXCTC[1:0]

OUTC2+

OUTC2–

REFCLKD+

TXLBC

Bit-Rate Clock

REFCLKD–

Transmit PLL

RECLCKD

TXRATED

OED[2..1]

Clock Multiplier D

SPDSELD

ENCBYPD

TXCLKOD

OED[2..1]

Character-Rate Clock D

TXERRD

TXCLKD

PABRSTD

TXBISTD

TXCKSELD

0

1

Phase-Align Buffer

Input Register

Encoder

BIST LFSR

OUTD1+

8

10

10

8B/10B

10

10

Shifter

OUTD1–

TXDD[7:0]

OUTD2+

2

OUTD2–

TXCTD[1:0]

TXLBD

Document #: 38-02097 Rev. *B

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Contents Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramTransmit Path Block Diagram Phase-Align rBuffeBist Lfsr PLL Device Configuration and Control Block = Internal SignalDevice Configura Tion and Control Interface Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsDevice Control Signals Name Characteristics Signal DescriptionStatus Signals Receive Path Clock SignalsUse Local Clock . When Reframe Mode Select Link Fault Indication OutputDevice Configuration and Control Bus Signals Control Write Enable .CYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit Bist Transmit ModesTransmit PLL Clock Multiplier Serial Line Receivers Signal Detect/Link FaultSerial Output Drivers CYV15G0404DXB Receive Data PathClock/Data Recovery ReclockerDeserializer/Framer Framer 10B/8B Decoder BlockReceive Bist Operation Bits DetectedReceive Elasticity Buffer Power ControlDevice Reset State Output BusDECBYPx = Decbyp = Device Configuration and Control InterfaceOutput Register Bit Assignments Signal Name Decoder Bypass Mode Signal Name Bus Weight Bit NameName Signal Description Device Configuration and Control Latch DescriptionsRxckseld RxckselaRxckselb RxckselcTxrated TxrateaTxrateb TxratecJtag Support Device Configuration StrategyDevice Control Latch Configuration Table Required stepReceive Elasticity buffer underrun/overrun Running disparity error . The character onLevel Select Inputs Normal character received . The valid DataRX PLL Bistdatacompare 000 / BistcommandcompareBisterror BiststartOperating Range CYV15G0404DXB DC Electrical CharacteristicsPower Up Requirements Maximum RatingsLvttl Output Test Load18 Power Supply TypAC Test Loads and Waveforms CML Output Test LoadParameter Description Min Max Unit CYV15G0404DXB AC Electrical CharacteristicsReceiver Lvttl Switching Characteristics Over the Operating REFCLKx Switching Characteristics Over the Operating RangeDevice Bus Configuration Write Timing Characteristics OverJtag Test Clock Characteristics Over the Operating Range Transmit Serial Outputs and TX PLL Characteristics OverParameter Description Test Conditions Max Unit CYV15G0404DXB HOTLink II Transmitter Switching WaveformsCapacitance20 Transmit Interface Write Timing REFCLKx selected TXRATEx =TXCTx10 Transmit InterfaceWrite Timing REFCLKx selected TXDx70REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Lvttl in PU VCC PowerReset Lvttl in PU CMLRXDC4 Lvttl OUT RXDC7 Lvttl OUTTXDB6 Lvttl TXDC0 LvttlTransmission Order X3.230 Codes and Notation ConventionsNotation Conventions 8B/10B Transmission CodeHex Value Code Violations Resulting from Prior ErrorsUse of the Tables for Generating Transmission Characters Valid Transmission Characters Data Byte NameAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB End of Frame Sequence Code Rule Violation and SVS Tx PatternViolation Pattern CYV15G0404DXB-BGI Package DiagramOrdering Information CYV15G0404DXB-BGCMethods to implement it New Data SheetAGT UKK/VED