Cypress CYV15G0404DXB manual REFCLKx RXDx70, RXSTx20 TXERRx36

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CYV15G0404DXB

Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver

Receive Interface Read Timing REFCLKx Selected full rate RXCLKx±

REFCLKx

RXDx[7:0],

RXSTx[2:0],

TXERRx[36]

RXCLKx

tREFCLK

tREFH tREFL

tRREFDA

tRREFDW

tREFxDV+

tREFxDV–

tRREFDW

Notes

34.The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLKx±.

35.The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input.

36.TXERRx is synchronous to RXCLKx only when RXCLKx is selected as REFCLK.

Receive Interface Read Timing REFCLKx Selected half rate RXCLKx±

REFCLKx

RXDx[7:0], RXSTx[2:0],

TXERRx[36]

tREFH

tRREFDA

tREFCLK tREFL

tRREFDA tRREFDW

tRREFDW

tREFxDV+					tREFxDV–

RXCLKx

Note 37

Receive Interface Read Timing Recovered Clock selected RXRATEx = 0

RXCLKx+

RXCLKx-

RXDx[7:0],

RXSTx[2:0],

tRXCLKP

tRXDV–

tRXDV+

Document #: 38-02097 Rev. *B

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description CYV15G0404DXB Transceiver Logic Block Diagram Phase Elasticity Align Buffer Encoder Decoder 8B/10B FramerBist Lfsr Transmit Path Block DiagramPhase-Align rBuffe PLL Device Configura Tion and Control Interface Device Configuration and Control Block= Internal Signal Pin Configuration Top View Pin Configuration Bottom View Transmit Path Clock Signals Pin Definitions CYV15G0404DXB Quad HOTLink II TransceiverName Characteristics Signal Description Status SignalsReceive Path Clock Signals Device Control SignalsUse Local Clock . When Link Fault Indication Output Device Configuration and Control Bus SignalsControl Write Enable . Reframe Mode SelectCYV15G0404DXB HOTLink II Operation CYV15G0404DXB Transmit Data PathEncoder Data EncodingTransmit PLL Clock Multiplier Transmit BistTransmit Modes Signal Detect/Link Fault Serial Output DriversCYV15G0404DXB Receive Data Path Serial Line ReceiversDeserializer/Framer Clock/Data RecoveryReclocker 10B/8B Decoder Block Receive Bist OperationBits Detected FramerPower Control Device Reset StateOutput Bus Receive Elasticity BufferDevice Configuration and Control Interface Output Register Bit Assignments Signal NameDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Device Configuration and Control Latch Descriptions Name Signal DescriptionRxcksela RxckselbRxckselc RxckseldTxratea TxratebTxratec TxratedDevice Configuration Strategy Device Control Latch Configuration TableRequired step Jtag SupportRunning disparity error . The character on Level Select InputsNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBistdatacompare 000 / Bistcommandcompare BisterrorBiststart RX PLLCYV15G0404DXB DC Electrical Characteristics Power Up RequirementsMaximum Ratings Operating RangePower Supply Typ AC Test Loads and WaveformsCML Output Test Load Lvttl Output Test Load18CYV15G0404DXB AC Electrical Characteristics Receiver Lvttl Switching Characteristics Over the OperatingREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitBus Configuration Write Timing Characteristics Over Jtag Test Clock Characteristics Over the Operating RangeTransmit Serial Outputs and TX PLL Characteristics Over DeviceCYV15G0404DXB HOTLink II Transmitter Switching Waveforms Capacitance20Transmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitTransmit Interface Write Timing REFCLKx selectedTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing VCC Power Reset Lvttl in PUCML Lvttl in PURXDC7 Lvttl OUT TXDB6 LvttlTXDC0 Lvttl RXDC4 Lvttl OUTX3.230 Codes and Notation Conventions Notation Conventions8B/10B Transmission Code Transmission OrderCode Violations Resulting from Prior Errors Use of the Tables for Generating Transmission CharactersValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Name Abcdei fghjData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Violation Pattern End of Frame SequenceCode Rule Violation and SVS Tx Pattern Package Diagram Ordering InformationCYV15G0404DXB-BGC CYV15G0404DXB-BGINew Data Sheet AGTUKK/VED Methods to implement it