Cypress CYV15G0404DXB manual

Page 41

CYV15G0404DXB

Table 14.	Valid Data Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)

Data	Bits	Current RD		−	Current RD+			Data	Bits		−	Current RD+
Byte	Bits	Current RD			Current RD+			Byte	Bits		Current RD	Current RD+
Name	HGF EDCBA	abcdei fghj			abcdei fghj			Name	HGF EDCBA		abcdei fghj	abcdei fghj
D0.6	110 00000	100111	0110		011000	0110		D0.7	111 00000		100111 0001	011000 1110
D1.6	110 00001	011101	0110		100010	0110		D1.7	111 00001		011101 0001	100010 1110
D2.6	110 00010	101101	0110		010010	0110		D2.7	111 00010		101101 0001	010010 1110
D3.6	110 00011	110001	0110		110001	0110		D3.7	111 00011		110001 1110	110001 0001
D4.6	110 00100	110101	0110		001010	0110		D4.7	111 00100		110101 0001	001010 1110
D5.6	110 00101	101001	0110		101001	0110		D5.7	111 00101		101001 1110	101001 0001
D6.6	110 00110	011001	0110		011001	0110		D6.7	111 00110		011001 1110	011001 0001
D7.6	110 00111	111000	0110		000111	0110		D7.7	111 00111		111000 1110	000111 0001
D8.6	110 01000	111001	0110		000110	0110		D8.7	111 01000		111001 0001	000110 1110
D9.6	110 01001	100101	0110		100101	0110		D9.7	111 01001		100101 1110	100101 0001
D10.6	110 01010	010101	0110		010101	0110		D10.7	111	01010	010101 1110	010101 0001
D11.6	110 01011	110100	0110		110100	0110		D11.7	111	01011	110100 1110	110100 1000
D12.6	110 01100	001101	0110		001101	0110		D12.7	111	01100	001101 1110	001101 0001
D13.6	110 01101	101100	0110		101100	0110		D13.7	111	01101	101100 1110	101100 1000
D14.6	110 01110	011100	0110		011100	0110		D14.7	111	01110	011100 1110	011100 1000
D15.6	110 01111	010111	0110		101000	0110		D15.7	111	01111	010111 0001	101000 1110
D16.6	110 10000	011011	0110		100100	0110		D16.7	111	10000	011011 0001	100100 1110
D17.6	110 10001	100011	0110		100011	0110		D17.7	111	10001	100011 0111	100011 0001
D18.6	110 10010	010011	0110		010011	0110		D18.7	111	10010	010011 0111	010011 0001
D19.6	110 10011	110010	0110		110010	0110		D19.7	111	10011	110010 1110	110010 0001
D20.6	110 10100	001011	0110		001011	0110		D20.7	111	10100	001011 0111	001011 0001
D21.6	110 10101	101010	0110		101010	0110		D21.7	111	10101	101010 1110	101010 0001
D22.6	110 10110	011010	0110		011010	0110		D22.7	111	10110	011010 1110	011010 0001
D23.6	110 10111	111010	0110		000101	0110		D23.7	111	10111	111010 0001	000101 1110
D24.6	110 11000	110011	0110		001100	0110		D24.7	111	11000	110011 0001	001100 1110
D25.6	110 11001	100110	0110		100110	0110		D25.7	111	11001	100110 1110	100110 0001
D26.6	110 11010	010110	0110		010110	0110		D26.7	111	11010	010110 1110	010110 0001
D27.6	110 11011	110110	0110		001001	0110		D27.7	111	11011	110110 0001	001001 1110
D28.6	110 11100	001110	0110		001110	0110		D28.7	111	11100	001110 1110	001110 0001
D29.6	110 11101	101110	0110		010001	0110		D29.7	111	11101	101110 0001	010001 1110
D30.6	110 11110	011110	0110		100001	0110		D30.7	111	11110	011110 0001	100001 1110
D31.6	110 11111	101011	0110		010100	0110		D31.7	111	11111	101011 0001	010100 1110
Document #: 38-02097 Rev. *B												Page 41 of 44

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description Phase Elasticity Align Buffer Encoder Decoder 8B/10B Framer CYV15G0404DXB Transceiver Logic Block DiagramBist Lfsr Transmit Path Block DiagramPhase-Align rBuffe PLL Device Configura Tion and Control Interface Device Configuration and Control Block= Internal Signal Pin Configuration Top View Pin Configuration Bottom View Pin Definitions CYV15G0404DXB Quad HOTLink II Transceiver Transmit Path Clock SignalsStatus Signals Name Characteristics Signal DescriptionReceive Path Clock Signals Device Control SignalsUse Local Clock . When Device Configuration and Control Bus Signals Link Fault Indication OutputControl Write Enable . Reframe Mode SelectCYV15G0404DXB Transmit Data Path CYV15G0404DXB HOTLink II OperationData Encoding EncoderTransmit PLL Clock Multiplier Transmit BistTransmit Modes Serial Output Drivers Signal Detect/Link FaultCYV15G0404DXB Receive Data Path Serial Line ReceiversDeserializer/Framer Clock/Data RecoveryReclocker Receive Bist Operation 10B/8B Decoder BlockBits Detected FramerDevice Reset State Power ControlOutput Bus Receive Elasticity BufferOutput Register Bit Assignments Signal Name Device Configuration and Control InterfaceDecoder Bypass Mode Signal Name Bus Weight Bit Name DECBYPx = Decbyp =Name Signal Description Device Configuration and Control Latch DescriptionsRxckselb RxckselaRxckselc RxckseldTxrateb TxrateaTxratec TxratedDevice Control Latch Configuration Table Device Configuration StrategyRequired step Jtag SupportLevel Select Inputs Running disparity error . The character onNormal character received . The valid Data Receive Elasticity buffer underrun/overrunBisterror Bistdatacompare 000 / BistcommandcompareBiststart RX PLLPower Up Requirements CYV15G0404DXB DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Power Supply TypCML Output Test Load Lvttl Output Test Load18Receiver Lvttl Switching Characteristics Over the Operating CYV15G0404DXB AC Electrical CharacteristicsREFCLKx Switching Characteristics Over the Operating Range Parameter Description Min Max UnitJtag Test Clock Characteristics Over the Operating Range Bus Configuration Write Timing Characteristics OverTransmit Serial Outputs and TX PLL Characteristics Over DeviceCapacitance20 CYV15G0404DXB HOTLink II Transmitter Switching WaveformsTransmit Interface Write Timing REFCLKx selected TXRATEx = Parameter Description Test Conditions Max UnitWrite Timing REFCLKx selected Transmit InterfaceTXDx70 TXCTx10REFCLKx RXDx70, RXSTx20 TXERRx36 Bus Configuration Write Timing Reset Lvttl in PU VCC PowerCML Lvttl in PUTXDB6 Lvttl RXDC7 Lvttl OUTTXDC0 Lvttl RXDC4 Lvttl OUTNotation Conventions X3.230 Codes and Notation Conventions8B/10B Transmission Code Transmission OrderUse of the Tables for Generating Transmission Characters Code Violations Resulting from Prior ErrorsValid Transmission Characters Data Byte Name Hex ValueAbcdei fghj Abcdei fghj NameData Bits Current RD Current RD+ Byte Name CYV15G0404DXB CYV15G0404DXB Violation Pattern End of Frame SequenceCode Rule Violation and SVS Tx Pattern Ordering Information Package DiagramCYV15G0404DXB-BGC CYV15G0404DXB-BGIAGT New Data SheetUKK/VED Methods to implement it